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[76.173.164.138]) by smtp.gmail.com with ESMTPSA id z127sm27767966pfb.72.2018.04.24.18.23.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Apr 2018 18:23:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HW2lFqjkdeznoEnZz0wGEReab483/vCLPZX1Ws3Xa70=; b=Sp7hZlMDs/U5mktye+I5j7q73ma39bQNztjq3ljHg1VHhm3nkxLMbsLKe5+e7CGRNY fOwV6TFyYaoOXi0lNV4Uag2lpMFn9u9OWuo4teP359AeAX8x1reR+jpefS6Shj7vX936 vRNbyUi6eBx1oOivzb+KPCAK/NBc8KDz/KEZI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HW2lFqjkdeznoEnZz0wGEReab483/vCLPZX1Ws3Xa70=; b=sTcG75z9CLEML8V/CEkOMSA+hTQ3pLaRM3VI1INirh7EoA8onQFCtZoK5ihaJ46ep/ X4yDNZ8tae7lKbeLIQ45N/OnN4wQLJIdDfvWd/claY/RysIO5mnZOvnN6aattY/z5iXr RGry5irIj5ArxJ0SLE3zp50ddAoGO9lcmAFmtTKcwuGyLFLPVhg4qxadclcCuUn+FBag g9POAb8O81M4R7m82zPNVhsJa6NMCPWyFAh4bA7h0RG+uM+4Rjf1XWw+rSPySOxwos8Y Cjk9Mlz+Z6M6I+x64zQ7K+axOC3S8mhGNlQyr1TXD3W/dMCpPlrCYmF+BDhIdqqPPJFy aymg== X-Gm-Message-State: ALQs6tAD1w+Z1RHiJR4lH85WO1otteBK2e2Vt5Ow3/TEDY0mhCl51E4C cjIv3Dz8i3vnSeI+aHs2lseFiPAcf98= X-Google-Smtp-Source: AIpwx49cOn3SvhoMj7Zim991FBoZeXiK52dZCj5zbCi4wN/ayM/1vxegqY5T6TulkopM3TmvV+3S9A== X-Received: by 10.99.143.22 with SMTP id n22mr21290654pgd.394.1524619392345; Tue, 24 Apr 2018 18:23:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 24 Apr 2018 15:22:54 -1000 Message-Id: <20180425012300.14698-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425012300.14698-1-richard.henderson@linaro.org> References: <20180425012300.14698-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 3/9] target/arm: Fix float16 to/from int16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The instruction "ucvtf v0.4h, v04h, #2", with input 0x8000u, overflows the intermediate float16 to infinity before we have a chance to scale the output. Use float64 as the intermediate type so that no input argument (uint32_t in this case) can overflow or round before scaling. Given the declared argument, the signed int32_t function has the same problem. When converting from float16 to integer, using u/int32_t instead of u/int16_t means that the bounding is incorrect. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/helper.h | 4 ++-- target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++++++++= ++-- target/arm/translate-a64.c | 4 ++-- 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b3ae394b4f..eafd5d746b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -149,8 +149,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, pt= r) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) diff --git a/target/arm/helper.c b/target/arm/helper.c index ea09510599..743f34bd0a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11409,11 +11409,60 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) VFP_CONV_FIX(uh, s, 32, 32, uint16) VFP_CONV_FIX(ul, s, 32, 32, uint32) VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) -VFP_CONV_FIX_A64(sl, h, 16, 32, int32) -VFP_CONV_FIX_A64(ul, h, 16, 32, uint32) + #undef VFP_CONV_FIX #undef VFP_CONV_FIX_FLOAT #undef VFP_CONV_FLOAT_FIX_ROUND +#undef VFP_CONV_FIX_A64 + +/* Conversion to/from f16 can overflow to infinity before/after scaling. + * Therefore we convert to f64 (which does not round), scale, + * and then convert f64 to f16 (which may round). + */ + +static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) +{ + return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst); +} + +float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst); +} + +float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) +{ + return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); +} + +static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) +{ + if (unlikely(float16_is_any_nan(f))) { + float_raise(float_flag_invalid, fpst); + return 0; + } else { + int old_exc_flags =3D get_float_exception_flags(fpst); + float64 ret; + + ret =3D float16_to_float64(f, true, fpst); + ret =3D float64_scalbn(ret, shift, fpst); + old_exc_flags |=3D get_float_exception_flags(fpst) + & float_flag_input_denormal; + set_float_exception_flags(old_exc_flags, fpst); + + return ret; + } +} + +uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst); +} + +uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) +{ + return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); +} =20 /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e2d11998bd..b27892d971 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7181,9 +7181,9 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, switch (size) { case MO_16: if (is_u) { - fn =3D gen_helper_vfp_toulh; + fn =3D gen_helper_vfp_touhh; } else { - fn =3D gen_helper_vfp_toslh; + fn =3D gen_helper_vfp_toshh; } break; case MO_32: --=20 2.14.3