From nobody Wed Oct 29 09:06:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524619496400489.31640937576753; Tue, 24 Apr 2018 18:24:56 -0700 (PDT) Received: from localhost ([::1]:33305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fB9Au-0004sN-1z for importer@patchew.org; Tue, 24 Apr 2018 21:24:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fB99N-0003ye-KO for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fB99M-0007CW-2l for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:13 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:37596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fB99L-0007Ai-Ss for qemu-devel@nongnu.org; Tue, 24 Apr 2018 21:23:12 -0400 Received: by mail-pf0-x242.google.com with SMTP id p6so13745898pfn.4 for ; Tue, 24 Apr 2018 18:23:11 -0700 (PDT) Received: from cloudburst.twiddle.net.com (cpe-76-173-164-138.hawaii.res.rr.com. [76.173.164.138]) by smtp.gmail.com with ESMTPSA id z127sm27767966pfb.72.2018.04.24.18.23.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Apr 2018 18:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OQzui9EuCc9nQfaD/b7sJPE8M560QcmRDcjPpX30vuA=; b=D/ljD++Jocv+2Cv2kxtC04HPH1FmUTP4xsWSl4R3bAA+Hr2356hh/KEU0qxlgYwzGt y5RYN6QXmPwnaEim6LIwwPBPPxzSfVt2HEpEWL6ajf+TvIN8e1voBXKicxlnc5S+ONiP hoLB4wBgxBM75hpjTTkT8F+mjXNz91uHvOtas= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OQzui9EuCc9nQfaD/b7sJPE8M560QcmRDcjPpX30vuA=; b=AHYEU4gdHWFrZZWMNsmP3MlFf2at1I+qFv+32iz2B+anx55T9/e/xunFfi+7WTRXNO 40Zll85nMp6CX6+Iyj1PefzZzcnfW1/TlmFZ2NlZ+4gLypAMa/SUN33AVR0yoM7jx1v6 4xY/jOa5BzgP3VZLCoyEDxRm/d6597PmCs/X6sYAQwsGpMT4poGu+I2eI9C2SCLeuwOd d6Mji8LIVuS2egDN5j7Gq+6oD4UBIMaU2cdpmuIcUP0clNsKcCaUAB3Czk4QLUls8sCl LHrzvWDW/+raZ7PWbPU+9F9f8KsWmpjzxYHl3+efOA8mwkzQ+w7s9hWrDpJtFzRm+nBr Keyg== X-Gm-Message-State: ALQs6tCmqJbdMz8S7VYMcA8vq+kn5yafOypA9W7vhgxF7MzDEJfLIG0H MmZC8PxiSmidk4gdj7Ye8OW5FRlIEqM= X-Google-Smtp-Source: AIpwx489X10Jj3GSC3nZOrAmc66oLEm+W3OSghKMw/FnSdaqzcs3fyLLnW1339TsyLJbiFjWQMTtsg== X-Received: by 2002:a17:902:6986:: with SMTP id l6-v6mr27011947plk.209.1524619390695; Tue, 24 Apr 2018 18:23:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 24 Apr 2018 15:22:53 -1000 Message-Id: <20180425012300.14698-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425012300.14698-1-richard.henderson@linaro.org> References: <20180425012300.14698-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 2/9] target/arm: Implement vector shifted FCVT for fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" While we have some of the scalar paths for FCVT for fp16, we failed to decode the fp16 version of these instructions. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 46 insertions(+), 19 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c92e052686..e2d11998bd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7120,19 +7120,28 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, bool is_q, bool is_u, int immh, int immb, int rn, int r= d) { - bool is_double =3D extract32(immh, 3, 1); int immhb =3D immh << 3 | immb; - int fracbits =3D (is_double ? 128 : 64) - immhb; - int pass; + int pass, size, fracbits; TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_rmode, tcg_shift; =20 - if (!extract32(immh, 2, 2)) { - unallocated_encoding(s); - return; - } - - if (!is_scalar && !is_q && is_double) { + if (immh & 0x8) { + size =3D MO_64; + if (!is_scalar && !is_q) { + unallocated_encoding(s); + return; + } + } else if (immh & 0x4) { + size =3D MO_32; + } else if (immh & 0x2) { + size =3D MO_16; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + } else { + /* Should have split out AdvSIMD modified immediate earlier. */ + assert(immh =3D=3D 1); unallocated_encoding(s); return; } @@ -7144,11 +7153,12 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - tcg_fpstatus =3D get_fpstatus_ptr(false); + tcg_fpstatus =3D get_fpstatus_ptr(size =3D=3D MO_16); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + fracbits =3D (16 << size) - immhb; tcg_shift =3D tcg_const_i32(fracbits); =20 - if (is_double) { + if (size =3D=3D 3) { int maxpass =3D is_scalar ? 1 : 2; =20 for (pass =3D 0; pass < maxpass; pass++) { @@ -7165,20 +7175,37 @@ static void handle_simd_shift_fpint_conv(DisasConte= xt *s, bool is_scalar, } clear_vec_high(s, is_q, rd); } else { - int maxpass =3D is_scalar ? 1 : is_q ? 4 : 2; + void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); + int maxpass =3D is_scalar ? 1 : (8 << is_q >> size); + + switch (size) { + case MO_16: + if (is_u) { + fn =3D gen_helper_vfp_toulh; + } else { + fn =3D gen_helper_vfp_toslh; + } + break; + case MO_32: + if (is_u) { + fn =3D gen_helper_vfp_touls; + } else { + fn =3D gen_helper_vfp_tosls; + } + break; + default: + g_assert_not_reached(); + } + for (pass =3D 0; pass < maxpass; pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); - if (is_u) { - gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstat= us); - } else { - gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstat= us); - } + read_vec_element_i32(s, tcg_op, rn, pass, size); + fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); if (is_scalar) { write_fp_sreg(s, rd, tcg_op); } else { - write_vec_element_i32(s, tcg_op, rd, pass, MO_32); + write_vec_element_i32(s, tcg_op, rd, pass, size); } tcg_temp_free_i32(tcg_op); } --=20 2.14.3