From nobody Wed Oct 29 20:35:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524606709809671.7588662379467; Tue, 24 Apr 2018 14:51:49 -0700 (PDT) Received: from localhost ([::1]:60969 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fB5qm-0006b2-Tb for importer@patchew.org; Tue, 24 Apr 2018 17:51:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fB5lQ-0002sS-C4 for qemu-devel@nongnu.org; Tue, 24 Apr 2018 17:46:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fB5lN-00077R-Vo for qemu-devel@nongnu.org; Tue, 24 Apr 2018 17:46:16 -0400 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:53832 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fB5lN-00077L-PG for qemu-devel@nongnu.org; Tue, 24 Apr 2018 17:46:13 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4B617EC013; Tue, 24 Apr 2018 21:46:12 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-175.rdu2.redhat.com [10.10.120.175]) by smtp.corp.redhat.com (Postfix) with ESMTP id 14A0F2166BC6; Tue, 24 Apr 2018 21:46:10 +0000 (UTC) From: Laszlo Ersek To: qemu-devel@nongnu.org Date: Tue, 24 Apr 2018 23:45:50 +0200 Message-Id: <20180424214550.32549-7-lersek@redhat.com> In-Reply-To: <20180424214550.32549-1-lersek@redhat.com> References: <20180424214550.32549-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Tue, 24 Apr 2018 21:46:13 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.1]); Tue, 24 Apr 2018 21:46:13 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PATCH 6/6] qapi: discriminate CpuInfo[Fast] on SysEmuTarget, not CpuInfoArch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Markus Armbruster , Peter Crosthwaite Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a new field @target (of type @SysEmuTarget) to the outputs of the @query-cpus and @query-cpus-fast commands, which provides more information about the emulation target than the field @arch (of type @CpuInfoArch). Keep @arch for compatibility. Make @target the new discriminator for the @CpuInfo and @CpuInfoFast return structures. This lets us hoist @arch to @CpuInfoCommon, but it also requires some gymnastics in qmp_query_cpus() and qmp_query_cpus_fast(). In particular, conditional compilation cannot be removed, because each pair of CPU base arch structures, such as X86CPU/CPUX86State, PowerPCCPU/CPUPPCState, SPARCCPU/CPUSPARCState, is only visible when building QEMU for a target that maps to that CPU base arch. Cc: Eric Blake Cc: Markus Armbruster Cc: Paolo Bonzini Cc: Peter Crosthwaite Cc: Richard Henderson Signed-off-by: Laszlo Ersek --- Notes: PATCHv1: =20 - new patch qapi/misc.json | 118 ++++++++++++++++++------- cpus.c | 275 ++++++++++++++++++++++++++++++++++++++++++-----------= ---- 2 files changed, 291 insertions(+), 102 deletions(-) diff --git a/qapi/misc.json b/qapi/misc.json index d7b776a5af37..98c15880f9f0 100644 --- a/qapi/misc.json +++ b/qapi/misc.json @@ -361,77 +361,105 @@ # Collects fields common to @CpuInfoBase and @CpuInfoFastBase; that is, # fields that are shared by @query-cpus and @query-cpus-fast, and not # specific to the target architecture. # # @qom-path: path to the CPU object in the QOM tree (since 2.4) # # @thread-id: ID of the underlying host thread # # @props: properties describing which node/socket/core/thread the # virtual CPU belongs to, if supported by the board (since 2.10) # +# @arch: base architecture of the cpu (since 2.6) +# # Since: 2.13 ## { 'struct' : 'CpuInfoCommon', 'data' : { 'qom-path' : 'str', 'thread-id' : 'int', - '*props' : 'CpuInstanceProperties' } } + '*props' : 'CpuInstanceProperties', + 'arch' : 'CpuInfoArch' } } =20 ## # @CpuInfoBase: # # Extends @CpuInfoCommon with fields that are specific to the @query-cpus # command, but not specific to the target architecture. # # @CPU: the index of the virtual CPU # # @current: this only exists for backwards compatibility and should be ign= ored # # @halted: true if the virtual CPU is in the halt state. Halt usually ref= ers # to a processor specific low power mode. # -# @arch: architecture of the cpu, which determines which additional fields -# will be listed (since 2.6) +# @target: the QEMU system emulation target, which is more specific than +# @arch and determines which additional fields will be listed +# # # Since: 2.13 # # Notes: @halted is a transient state that changes frequently. By the tim= e the # data is sent to the client, the guest may no longer be halted. -# Moreover, @arch cannot be moved up to @CpuInfoCommon because +# Moreover, @target cannot be moved up to @CpuInfoCommon because # that would prevent its use as the discriminator in @CpuInfo. ## { 'struct' : 'CpuInfoBase', 'base' : 'CpuInfoCommon', 'data' : { 'CPU' : 'int', 'current' : 'bool', 'halted' : 'bool', - 'arch' : 'CpuInfoArch' } } + 'target' : 'SysEmuTarget' } } =20 ## # @CpuInfo: # # Information about a virtual CPU # # Since: 0.14.0 ## -{ 'union': 'CpuInfo', - 'base': 'CpuInfoBase', - 'discriminator': 'arch', - 'data': { 'x86': 'CpuInfoX86', - 'sparc': 'CpuInfoSPARC', - 'ppc': 'CpuInfoPPC', - 'mips': 'CpuInfoMIPS', - 'tricore': 'CpuInfoTricore', - 's390': 'CpuInfoS390', - 'riscv': 'CpuInfoRISCV', - 'other': 'CpuInfoOther' } } +{ 'union' : 'CpuInfo', + 'base' : 'CpuInfoBase', + 'discriminator' : 'target', + 'data' : { 'i386' : 'CpuInfoX86', + 'x86_64' : 'CpuInfoX86', + 'sparc' : 'CpuInfoSPARC', + 'sparc64' : 'CpuInfoSPARC', + 'ppc' : 'CpuInfoPPC', + 'ppcemb' : 'CpuInfoPPC', + 'ppc64' : 'CpuInfoPPC', + 'mips' : 'CpuInfoMIPS', + 'mipsel' : 'CpuInfoMIPS', + 'mips64' : 'CpuInfoMIPS', + 'mips64el' : 'CpuInfoMIPS', + 'tricore' : 'CpuInfoTricore', + 's390x' : 'CpuInfoS390', + 'riscv32' : 'CpuInfoRISCV', + 'riscv64' : 'CpuInfoRISCV', + 'aarch64' : 'CpuInfoOther', + 'alpha' : 'CpuInfoOther', + 'arm' : 'CpuInfoOther', + 'cris' : 'CpuInfoOther', + 'hppa' : 'CpuInfoOther', + 'lm32' : 'CpuInfoOther', + 'm68k' : 'CpuInfoOther', + 'microblaze' : 'CpuInfoOther', + 'microblazeel' : 'CpuInfoOther', + 'moxie' : 'CpuInfoOther', + 'nios2' : 'CpuInfoOther', + 'or1k' : 'CpuInfoOther', + 'sh4' : 'CpuInfoOther', + 'sh4eb' : 'CpuInfoOther', + 'unicore32' : 'CpuInfoOther', + 'xtensa' : 'CpuInfoOther', + 'xtensaeb' : 'CpuInfoOther' } } =20 ## # @CpuInfoX86: # # Additional information about a virtual i386 or x86_64 CPU # # @pc: the 64-bit instruction pointer # # Since: 2.6 ## { 'struct': 'CpuInfoX86', 'data': { 'pc': 'int' } } @@ -543,84 +571,110 @@ # # Example: # # -> { "execute": "query-cpus" } # <- { "return": [ # { # "CPU":0, # "current":true, # "halted":false, # "qom-path":"/machine/unattached/device[0]", # "arch":"x86", +# "target":"x86_64", # "pc":3227107138, # "thread-id":3134 # }, # { # "CPU":1, # "current":false, # "halted":true, # "qom-path":"/machine/unattached/device[2]", # "arch":"x86", +# "target":"x86_64", # "pc":7108165, # "thread-id":3135 # } # ] # } # # Notes: This interface is deprecated (since 2.12.0), and it is strongly # recommended that you avoid using it. Use @query-cpus-fast to # obtain information about virtual CPUs. # ## { 'command': 'query-cpus', 'returns': ['CpuInfo'] } =20 ## # @CpuInfoFastBase: # # Extends @CpuInfoCommon with fields that are specific to the # @query-cpus-fast command, but not specific to the target architecture. # # @cpu-index: index of the virtual CPU # -# @arch: architecture of the cpu, which determines which additional fields -# will be listed +# @target: the QEMU system emulation target, which is more specific than +# @arch and determines which additional fields will be listed # # Since: 2.13 # -# Notes: @arch cannot be moved up to @CpuInfoCommon because that would +# Notes: @target cannot be moved up to @CpuInfoCommon because that would # prevent its use as the discriminator in @CpuInfoFast. ## { 'struct' : 'CpuInfoFastBase', 'base' : 'CpuInfoCommon', 'data' : { 'cpu-index' : 'int', - 'arch' : 'CpuInfoArch' } } + 'target' : 'SysEmuTarget' } } =20 ## # @CpuInfoFast: # # Information about a virtual CPU # # Since: 2.12 # ## -{ 'union': 'CpuInfoFast', - 'base': 'CpuInfoFastBase', - 'discriminator': 'arch', - 'data': { 'x86': 'CpuInfoOther', - 'sparc': 'CpuInfoOther', - 'ppc': 'CpuInfoOther', - 'mips': 'CpuInfoOther', - 'tricore': 'CpuInfoOther', - 's390': 'CpuInfoS390', - 'riscv': 'CpuInfoOther', - 'other': 'CpuInfoOther' } } +{ 'union' : 'CpuInfoFast', + 'base' : 'CpuInfoFastBase', + 'discriminator' : 'target', + 'data' : { 'i386' : 'CpuInfoOther', + 'x86_64' : 'CpuInfoOther', + 'sparc' : 'CpuInfoOther', + 'sparc64' : 'CpuInfoOther', + 'ppc' : 'CpuInfoOther', + 'ppcemb' : 'CpuInfoOther', + 'ppc64' : 'CpuInfoOther', + 'mips' : 'CpuInfoOther', + 'mipsel' : 'CpuInfoOther', + 'mips64' : 'CpuInfoOther', + 'mips64el' : 'CpuInfoOther', + 'tricore' : 'CpuInfoOther', + 's390x' : 'CpuInfoS390', + 'riscv32' : 'CpuInfoOther', + 'riscv64' : 'CpuInfoOther', + 'aarch64' : 'CpuInfoOther', + 'alpha' : 'CpuInfoOther', + 'arm' : 'CpuInfoOther', + 'cris' : 'CpuInfoOther', + 'hppa' : 'CpuInfoOther', + 'lm32' : 'CpuInfoOther', + 'm68k' : 'CpuInfoOther', + 'microblaze' : 'CpuInfoOther', + 'microblazeel' : 'CpuInfoOther', + 'moxie' : 'CpuInfoOther', + 'nios2' : 'CpuInfoOther', + 'or1k' : 'CpuInfoOther', + 'sh4' : 'CpuInfoOther', + 'sh4eb' : 'CpuInfoOther', + 'unicore32' : 'CpuInfoOther', + 'xtensa' : 'CpuInfoOther', + 'xtensaeb' : 'CpuInfoOther' } } =20 ## # @query-cpus-fast: # # Returns information about all virtual CPUs. This command does not # incur a performance penalty and should be used in production # instead of query-cpus. # # Returns: list of @CpuInfoFast # # Since: 2.12 @@ -630,33 +684,35 @@ # -> { "execute": "query-cpus-fast" } # <- { "return": [ # { # "thread-id": 25627, # "props": { # "core-id": 0, # "thread-id": 0, # "socket-id": 0 # }, # "qom-path": "/machine/unattached/device[0]", # "arch":"x86", +# "target":"x86_64", # "cpu-index": 0 # }, # { # "thread-id": 25628, # "props": { # "core-id": 0, # "thread-id": 0, # "socket-id": 1 # }, # "qom-path": "/machine/unattached/device[2]", # "arch":"x86", +# "target":"x86_64", # "cpu-index": 1 # } # ] # } ## { 'command': 'query-cpus-fast', 'returns': [ 'CpuInfoFast' ] } =20 ## # @IOThreadInfo: # # Information about an iothread diff --git a/cpus.c b/cpus.c index 60563a6d54ec..86eed0ffe796 100644 --- a/cpus.c +++ b/cpus.c @@ -2093,88 +2093,235 @@ int vm_stop_force_state(RunState state) } } =20 void list_cpus(FILE *f, fprintf_function cpu_fprintf, const char *optarg) { /* XXX: implement xxx_cpu_list for targets that still miss it */ #if defined(cpu_list) cpu_list(f, cpu_fprintf); #endif } =20 +static CpuInfoArch sysemu_target_to_cpuinfo_arch(SysEmuTarget target) +{ + /* + * The @SysEmuTarget -> @CpuInfoArch mapping below is based on the + * TARGET_ARCH -> TARGET_BASE_ARCH mapping in the "configure" script. + */ + switch (target) { + case SYS_EMU_TARGET_I386: + case SYS_EMU_TARGET_X86_64: + return CPU_INFO_ARCH_X86; + + case SYS_EMU_TARGET_PPC: + case SYS_EMU_TARGET_PPCEMB: + case SYS_EMU_TARGET_PPC64: + return CPU_INFO_ARCH_PPC; + + case SYS_EMU_TARGET_SPARC: + case SYS_EMU_TARGET_SPARC64: + return CPU_INFO_ARCH_SPARC; + + case SYS_EMU_TARGET_MIPS: + case SYS_EMU_TARGET_MIPSEL: + case SYS_EMU_TARGET_MIPS64: + case SYS_EMU_TARGET_MIPS64EL: + return CPU_INFO_ARCH_MIPS; + + case SYS_EMU_TARGET_TRICORE: + return CPU_INFO_ARCH_TRICORE; + + case SYS_EMU_TARGET_S390X: + return CPU_INFO_ARCH_S390; + + case SYS_EMU_TARGET_RISCV32: + case SYS_EMU_TARGET_RISCV64: + return CPU_INFO_ARCH_RISCV; + + default: + return CPU_INFO_ARCH_OTHER; + } +} + +static void cpustate_to_cpuinfo_x86(CpuInfoX86 *info, const CPUState *cpu) +{ +#ifdef TARGET_I386 + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + info->pc =3D env->eip + env->segs[R_CS].base; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_ppc(CpuInfoPPC *info, const CPUState *cpu) +{ +#ifdef TARGET_PPC + PowerPCCPU *ppc_cpu =3D POWERPC_CPU(cpu); + CPUPPCState *env =3D &ppc_cpu->env; + + info->nip =3D env->nip; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_sparc(CpuInfoSPARC *info, const CPUState *= cpu) +{ +#ifdef TARGET_SPARC + SPARCCPU *sparc_cpu =3D SPARC_CPU(cpu); + CPUSPARCState *env =3D &sparc_cpu->env; + + info->pc =3D env->pc; + info->npc =3D env->npc; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_mips(CpuInfoMIPS *info, const CPUState *cp= u) +{ +#ifdef TARGET_MIPS + MIPSCPU *mips_cpu =3D MIPS_CPU(cpu); + CPUMIPSState *env =3D &mips_cpu->env; + + info->PC =3D env->active_tc.PC; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_tricore(CpuInfoTricore *info, + const CPUState *cpu) +{ +#ifdef TARGET_TRICORE + TriCoreCPU *tricore_cpu =3D TRICORE_CPU(cpu); + CPUTriCoreState *env =3D &tricore_cpu->env; + + info->PC =3D env->PC; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_s390(CpuInfoS390 *info, const CPUState *cp= u) +{ +#ifdef TARGET_S390X + S390CPU *s390_cpu =3D S390_CPU(cpu); + CPUS390XState *env =3D &s390_cpu->env; + + info->cpu_state =3D env->cpu_state; +#else + abort(); +#endif +} + +static void cpustate_to_cpuinfo_riscv(CpuInfoRISCV *info, const CPUState *= cpu) +{ +#ifdef TARGET_RISCV + RISCVCPU *riscv_cpu =3D RISCV_CPU(cpu); + CPURISCVState *env =3D &riscv_cpu->env; + + info->pc =3D env->pc; +#else + abort(); +#endif +} + CpuInfoList *qmp_query_cpus(Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); MachineClass *mc =3D MACHINE_GET_CLASS(ms); CpuInfoList *head =3D NULL, *cur_item =3D NULL; + SysEmuTarget target =3D qapi_enum_parse(&SysEmuTarget_lookup, TARGET_N= AME, + -1, &error_abort); CPUState *cpu; =20 CPU_FOREACH(cpu) { CpuInfoList *info; -#if defined(TARGET_I386) - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; -#elif defined(TARGET_PPC) - PowerPCCPU *ppc_cpu =3D POWERPC_CPU(cpu); - CPUPPCState *env =3D &ppc_cpu->env; -#elif defined(TARGET_SPARC) - SPARCCPU *sparc_cpu =3D SPARC_CPU(cpu); - CPUSPARCState *env =3D &sparc_cpu->env; -#elif defined(TARGET_RISCV) - RISCVCPU *riscv_cpu =3D RISCV_CPU(cpu); - CPURISCVState *env =3D &riscv_cpu->env; -#elif defined(TARGET_MIPS) - MIPSCPU *mips_cpu =3D MIPS_CPU(cpu); - CPUMIPSState *env =3D &mips_cpu->env; -#elif defined(TARGET_TRICORE) - TriCoreCPU *tricore_cpu =3D TRICORE_CPU(cpu); - CPUTriCoreState *env =3D &tricore_cpu->env; -#elif defined(TARGET_S390X) - S390CPU *s390_cpu =3D S390_CPU(cpu); - CPUS390XState *env =3D &s390_cpu->env; -#endif =20 cpu_synchronize_state(cpu); =20 info =3D g_malloc0(sizeof(*info)); info->value =3D g_malloc0(sizeof(*info->value)); info->value->CPU =3D cpu->cpu_index; info->value->current =3D (cpu =3D=3D first_cpu); info->value->halted =3D cpu->halted; info->value->qom_path =3D object_get_canonical_path(OBJECT(cpu)); info->value->thread_id =3D cpu->thread_id; -#if defined(TARGET_I386) - info->value->arch =3D CPU_INFO_ARCH_X86; - info->value->u.x86.pc =3D env->eip + env->segs[R_CS].base; -#elif defined(TARGET_PPC) - info->value->arch =3D CPU_INFO_ARCH_PPC; - info->value->u.ppc.nip =3D env->nip; -#elif defined(TARGET_SPARC) - info->value->arch =3D CPU_INFO_ARCH_SPARC; - info->value->u.q_sparc.pc =3D env->pc; - info->value->u.q_sparc.npc =3D env->npc; -#elif defined(TARGET_MIPS) - info->value->arch =3D CPU_INFO_ARCH_MIPS; - info->value->u.q_mips.PC =3D env->active_tc.PC; -#elif defined(TARGET_TRICORE) - info->value->arch =3D CPU_INFO_ARCH_TRICORE; - info->value->u.tricore.PC =3D env->PC; -#elif defined(TARGET_S390X) - info->value->arch =3D CPU_INFO_ARCH_S390; - info->value->u.s390.cpu_state =3D env->cpu_state; -#elif defined(TARGET_RISCV) - info->value->arch =3D CPU_INFO_ARCH_RISCV; - info->value->u.riscv.pc =3D env->pc; -#else - info->value->arch =3D CPU_INFO_ARCH_OTHER; -#endif + info->value->arch =3D sysemu_target_to_cpuinfo_arch(target); + info->value->target =3D target; + + /* + * The @SysEmuTarget -> @CpuInfo mapping below is based on the + * TARGET_ARCH -> TARGET_BASE_ARCH mapping in the "configure" scri= pt. + */ + switch (target) { + case SYS_EMU_TARGET_I386: + cpustate_to_cpuinfo_x86(&info->value->u.i386, cpu); + break; + case SYS_EMU_TARGET_X86_64: + cpustate_to_cpuinfo_x86(&info->value->u.x86_64, cpu); + break; + + case SYS_EMU_TARGET_PPC: + cpustate_to_cpuinfo_ppc(&info->value->u.ppc, cpu); + break; + case SYS_EMU_TARGET_PPCEMB: + cpustate_to_cpuinfo_ppc(&info->value->u.ppcemb, cpu); + break; + case SYS_EMU_TARGET_PPC64: + cpustate_to_cpuinfo_ppc(&info->value->u.ppc64, cpu); + break; + + case SYS_EMU_TARGET_SPARC: + cpustate_to_cpuinfo_sparc(&info->value->u.q_sparc, cpu); + break; + case SYS_EMU_TARGET_SPARC64: + cpustate_to_cpuinfo_sparc(&info->value->u.sparc64, cpu); + break; + + case SYS_EMU_TARGET_MIPS: + cpustate_to_cpuinfo_mips(&info->value->u.q_mips, cpu); + break; + case SYS_EMU_TARGET_MIPSEL: + cpustate_to_cpuinfo_mips(&info->value->u.mipsel, cpu); + break; + case SYS_EMU_TARGET_MIPS64: + cpustate_to_cpuinfo_mips(&info->value->u.mips64, cpu); + break; + case SYS_EMU_TARGET_MIPS64EL: + cpustate_to_cpuinfo_mips(&info->value->u.mips64el, cpu); + break; + + case SYS_EMU_TARGET_TRICORE: + cpustate_to_cpuinfo_tricore(&info->value->u.tricore, cpu); + break; + + case SYS_EMU_TARGET_S390X: + cpustate_to_cpuinfo_s390(&info->value->u.s390x, cpu); + break; + + case SYS_EMU_TARGET_RISCV32: + cpustate_to_cpuinfo_riscv(&info->value->u.riscv32, cpu); + break; + case SYS_EMU_TARGET_RISCV64: + cpustate_to_cpuinfo_riscv(&info->value->u.riscv64, cpu); + break; + + default: + /* do nothing for @CpuInfoOther */ + break; + } + info->value->has_props =3D !!mc->cpu_index_to_instance_props; if (info->value->has_props) { CpuInstanceProperties *props; props =3D g_malloc0(sizeof(*props)); *props =3D mc->cpu_index_to_instance_props(ms, cpu->cpu_index); info->value->props =3D props; } =20 /* XXX: waiting for the qapi to support GSList */ if (!cur_item) { head =3D cur_item =3D info; @@ -2188,64 +2335,50 @@ CpuInfoList *qmp_query_cpus(Error **errp) } =20 /* * fast means: we NEVER interrupt vCPU threads to retrieve * information from KVM. */ CpuInfoFastList *qmp_query_cpus_fast(Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); MachineClass *mc =3D MACHINE_GET_CLASS(ms); CpuInfoFastList *head =3D NULL, *cur_item =3D NULL; + SysEmuTarget target =3D qapi_enum_parse(&SysEmuTarget_lookup, TARGET_N= AME, + -1, &error_abort); CPUState *cpu; -#if defined(TARGET_S390X) - S390CPU *s390_cpu; - CPUS390XState *env; -#endif =20 CPU_FOREACH(cpu) { CpuInfoFastList *info =3D g_malloc0(sizeof(*info)); info->value =3D g_malloc0(sizeof(*info->value)); =20 info->value->cpu_index =3D cpu->cpu_index; info->value->qom_path =3D object_get_canonical_path(OBJECT(cpu)); info->value->thread_id =3D cpu->thread_id; =20 info->value->has_props =3D !!mc->cpu_index_to_instance_props; if (info->value->has_props) { CpuInstanceProperties *props; props =3D g_malloc0(sizeof(*props)); *props =3D mc->cpu_index_to_instance_props(ms, cpu->cpu_index); info->value->props =3D props; } =20 -#if defined(TARGET_I386) - info->value->arch =3D CPU_INFO_ARCH_X86; -#elif defined(TARGET_PPC) - info->value->arch =3D CPU_INFO_ARCH_PPC; -#elif defined(TARGET_SPARC) - info->value->arch =3D CPU_INFO_ARCH_SPARC; -#elif defined(TARGET_MIPS) - info->value->arch =3D CPU_INFO_ARCH_MIPS; -#elif defined(TARGET_TRICORE) - info->value->arch =3D CPU_INFO_ARCH_TRICORE; -#elif defined(TARGET_S390X) - s390_cpu =3D S390_CPU(cpu); - env =3D &s390_cpu->env; - info->value->arch =3D CPU_INFO_ARCH_S390; - info->value->u.s390.cpu_state =3D env->cpu_state; -#elif defined(TARGET_RISCV) - info->value->arch =3D CPU_INFO_ARCH_RISCV; -#else - info->value->arch =3D CPU_INFO_ARCH_OTHER; -#endif + info->value->arch =3D sysemu_target_to_cpuinfo_arch(target); + info->value->target =3D target; + if (target =3D=3D SYS_EMU_TARGET_S390X) { + cpustate_to_cpuinfo_s390(&info->value->u.s390x, cpu); + } else { + /* do nothing for @CpuInfoOther */ + } + if (!cur_item) { head =3D cur_item =3D info; } else { cur_item->next =3D info; cur_item =3D info; } } =20 return head; } =20 --=20 2.14.1.3.gb7cf6e02401b