From nobody Mon Feb 9 05:01:06 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1524239743748859.1895438290554; Fri, 20 Apr 2018 08:55:43 -0700 (PDT) Received: from localhost ([::1]:39137 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YNz-0001BD-00 for importer@patchew.org; Fri, 20 Apr 2018 11:55:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJQ-000629-8R for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJM-0005wb-WC for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:00 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:38261) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJM-0005vZ-Lp for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:56 -0400 Received: by mail-wr0-x242.google.com with SMTP id h3-v6so24247423wrh.5 for ; Fri, 20 Apr 2018 08:50:56 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l53-v6sm7096855wrc.80.2018.04.20.08.50.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:52 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8A5193E0402; Fri, 20 Apr 2018 16:50:45 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IQUsxXl0UZdkYa7y532hBMAgXe8ET9AN63dldcNKruY=; b=DmfV74OTNzGMWxS+p4cXnNFdJj4QExgkV6dX9hX36LwVQTi7iyqeEYlrKUOWnU/F/9 Pu5dEyROFGvJLTY2wKA4qyhXFvnGlS3m0AQ25TuQ7a25PJvDTI4S6mC1Fq7JbenbXpPB HDmgcC4+xKXKbhMZIuP9dsh+cun1zNV5lJ2+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IQUsxXl0UZdkYa7y532hBMAgXe8ET9AN63dldcNKruY=; b=FddllCySgthYjVJc6gsIIF7RmVbwUzTCXbxQ3guUZP05eLeSTxw0znM4dCnQkReKq1 Q0WBVFAC1In06v8Nk+U7iLmDIqwBwXT6zvKLzCFxHDhn/z9Q8ZTx0rYGi77AENuptq3s GL42UQDe744pkmJGDQkl08Maqgcqp0ztCo3lZyaCf+vePpRj5FZDu444+cZ3yHLQ7gpq xsVICAegeKalYYNAVoB93q+b/fAWAwVp17YUrsVbxAl/qgDYI5TcFgR4TtQD+RySqqB4 bW/FGIbdZAG8vB2yUF9qOSTfGXo06eaqG7uUrcqbuyBr9SwjbdpyIjpY3ldBCF+CBGMG wUFw== X-Gm-Message-State: ALQs6tDH3XiLxb19or71Gr4OBTVyTONG36Rha3sAH6+WMoTCz+LnqD+s iMMs91WOkb9C/9mrzkOwLT/l5A== X-Google-Smtp-Source: AIpwx4++G3J6M7thqaSTyHF77aMirhs+ruNjnGq0pQIz1lB1MiNNyghxLxdRG0xrbCQwCuv0AI4avA== X-Received: by 2002:adf:b595:: with SMTP id c21-v6mr8682758wre.233.1524239455421; Fri, 20 Apr 2018 08:50:55 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:44 +0100 Message-Id: <20180420155045.18862-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RFC PATCH 5/6] accel/tcg: create store_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is a common helper for all stores (currently 1 and 2 byte operations). It takes a size and endian parameter. Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/softmmu.c | 244 ++++++++++++++------------------------------ 1 file changed, 79 insertions(+), 165 deletions(-) diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c index e6f93250f9..2be2d9025f 100644 --- a/accel/tcg/softmmu.c +++ b/accel/tcg/softmmu.c @@ -245,6 +245,10 @@ tcg_target_ulong __attribute__((flatten)) helper_be_ld= sw_mmu(CPUArchState *env, return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); } =20 +/* + * Store Helpers + */ + static inline void io_writeb(CPUArchState *env, size_t mmu_idx, size_t index, uint8_t val, @@ -255,86 +259,6 @@ static inline void io_writeb(CPUArchState *env, return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 1); } =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (1 - 1)) !=3D 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D (val); - io_writeb(env, mmu_idx, index, val, addr, retaddr); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (1 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 - >=3D TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + 1) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; - if (page2 !=3D (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 1, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i =3D 0; i < 1; ++i) { - /* Little-endian extract. */ - uint8_t val8 =3D val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; - - stb_p((uint8_t *)haddr, val); - - - -} - - - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ static inline void io_writew(CPUArchState *env, size_t mmu_idx, size_t index, uint16_t val, @@ -345,8 +269,9 @@ static inline void io_writew(CPUArchState *env, return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 2); } =20 -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +static void store_helper(CPUArchState *env, target_ulong addr, uint64_t va= l, + size_t size, bool big_endian, TCGMemOpIdx oi, + uintptr_t retaddr) { unsigned mmu_idx =3D get_mmuidx(oi); int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -363,7 +288,7 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulong = addr, uint16_t val, if ((addr & TARGET_PAGE_MASK) !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; @@ -371,20 +296,40 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulon= g addr, uint16_t val, =20 /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) !=3D 0) { + if ((addr & (size - 1)) !=3D 0) { goto do_unaligned_access; } =20 /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. = */ - val =3D (val); - io_writew(env, mmu_idx, index, val, addr, retaddr); + switch (size) { + case 1: + { + uint8_t wv =3D (val); + io_writeb(env, mmu_idx, index, wv, addr, retaddr); + break; + } + case 2: + { + uint16_t wv; + if (big_endian) { + wv =3D bswap16( (uint16_t) val); + } else { + wv =3D (val); + } + io_writew(env, mmu_idx, index, wv, addr, retaddr); + break; + } + default: + g_assert_not_reached(); + break; + } return; } =20 /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 >=3D TARGET_PAGE_SIZE)) { int i, index2; target_ulong page2, tlb_addr2; @@ -392,104 +337,73 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulo= ng addr, uint16_t val, /* Ensure the second page is in the TLB. Note that the first page is already guaranteed to be filled, and that the second page cannot evict the first. */ - page2 =3D (addr + 2) & TARGET_PAGE_MASK; + page2 =3D (addr + size) & TARGET_PAGE_MASK; index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; if (page2 !=3D (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, mmu_idx, retaddr); } =20 /* XXX: not efficient, but simple. */ /* This loop must go in the forward direction to avoid issues with self-modifying code in Windows 64-bit. */ - for (i =3D 0; i < 2; ++i) { - /* Little-endian extract. */ - uint8_t val8 =3D val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); + for (i =3D 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 =3D val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 =3D val >> (i * 8); + } + store_helper(env, addr + i, val8, 1, big_endian, oi, retaddr); } return; } =20 haddr =3D addr + env->tlb_table[mmu_idx][index].addend; =20 - - - stw_le_p((uint8_t *)haddr, val); - -} - - -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - !=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, - mmu_idx, retaddr); + switch(size) { + case 1: + stb_p((uint8_t *)haddr, val); + break; + case 2: + if (big_endian) { + stw_be_p((uint8_t *)haddr, val); + } else { + stw_le_p((uint8_t *)haddr, val); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; + break; + default: + g_assert_not_reached(); + break; } +} =20 - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) !=3D 0) { - goto do_unaligned_access; - } +void __attribute__((flatten)) helper_ret_stb_mmu(CPUArchState *env, + target_ulong addr, uint8_= t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 1, false, oi, retaddr); +} =20 - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. = */ - val =3D bswap16(val); - io_writew(env, mmu_idx, index, val, addr, retaddr); - return; - } =20 - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >=3D TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 =3D (addr + 2) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; - if (page2 !=3D (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, - mmu_idx, retaddr); - } +void __attribute__((flatten)) helper_le_stw_mmu(CPUArchState *env, + target_ulong addr, uint16_= t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 2, false, oi, retaddr); +} =20 - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i =3D 0; i < 2; ++i) { - /* Big-endian extract. */ - uint8_t val8 =3D val >> (((2 - 1) * 8) - (i * 8)); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); - } - return; - } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; - stw_be_p((uint8_t *)haddr, val); +void __attribute__((flatten)) helper_be_stw_mmu(CPUArchState *env, + target_ulong addr, uint16_= t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 2, true, oi, retaddr); } --=20 2.17.0