From nobody Mon Feb 9 18:44:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523949876198878.8526955256222; Tue, 17 Apr 2018 00:24:36 -0700 (PDT) Received: from localhost ([::1]:47962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8Kyh-0000Ij-AX for importer@patchew.org; Tue, 17 Apr 2018 03:24:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8Krv-0003TG-94 for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f8Krt-0008Vh-LH for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:35 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:60639) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f8Krs-0008TV-Vm; Tue, 17 Apr 2018 03:17:33 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40QGm73QB0z9s2B; Tue, 17 Apr 2018 17:17:27 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1523949447; bh=iNW3B4D/ZxUrGOvpYyZGRduYs64IcJDzDdTVwGThRkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HhIMb/+kMeT+Wy3fNZ3d0vfP5mUHFCtKFbQ1eoY+Wm5hGsY/GhmSn7adhuFPyvMOa /MWuQSyIqesF26qgwKVBck5yjhRZB82uWmb2cHeBpZFQxU11F4HGgLcqSHxfBMHz+Q PSZ/LHB0Q8MhTO9tESejwnPLOFvM4bS9pR23+QoY= From: David Gibson To: groug@kaod.org Date: Tue, 17 Apr 2018 17:17:20 +1000 Message-Id: <20180417071722.9399-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180417071722.9399-1-david@gibson.dropbear.id.au> References: <20180417071722.9399-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 08/10] spapr: Clean up handling of LPCR power-saving exit bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To prevent spurious wakeups on cpus that are supposed to be disabled, we need to clear the LPCR bits which control certain wakeup events. spapr_cpu_reset() has separate cases here for boot and non-boot (initially inactive) cpus. rtas_start_cpu() then turns the LPCR bits on when the non-boot cpus are activated. But explicit checks against first_cpu are not how we usually do things: instead spapr_cpu_reset() generally sets things up for non-boot (inactive) cpus, then spapr_machine_reset() and/or rtas_start_cpu() override as necessary. So, do that instead. Because the LPCR activation is identical for boot cpus and non-boot cpus just activated with rtas_start_cpu() we can put the code common in spapr_cpu_set_entry_state(). Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr_cpu_core.c | 22 +++++++--------------- hw/ppc/spapr_rtas.c | 4 ---- 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index ecd40dbf03..8be0265d04 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -52,28 +52,17 @@ static void spapr_cpu_reset(void *opaque) * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for * real mode accesses, which thankfully defaults to 0 and isn't * accessible in guest mode. + * + * Disable Power-saving mode Exit Cause exceptions for the CPU, so + * we don't get spurious wakups before an RTAS start-cpu call. */ - lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV); + lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm= ); lpcr |=3D LPCR_LPES0 | LPCR_LPES1; =20 /* Set RMLS to the max (ie, 16G) */ lpcr &=3D ~LPCR_RMLS; lpcr |=3D 1ull << LPCR_RMLS_SHIFT; =20 - /* Only enable Power-saving mode Exit Cause exceptions on the boot - * CPU. The RTAS command start-cpu will enable them on secondaries. - */ - if (cs =3D=3D first_cpu) { - lpcr |=3D pcc->lpcr_pm; - } - - /* Disable Power-saving mode Exit Cause exceptions for the CPU. - * This can cause issues when rebooting the guest if a secondary - * is awaken */ - if (cs !=3D first_cpu) { - lpcr &=3D ~pcc->lpcr_pm; - } - ppc_store_lpcr(cpu, lpcr); =20 /* Set a full AMOR so guest can use the AMR as it sees fit */ @@ -82,11 +71,14 @@ static void spapr_cpu_reset(void *opaque) =20 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) { + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 env->nip =3D SPAPR_ENTRY_POINT; env->gpr[3] =3D r3; CPU(cpu)->halted =3D 0; + /* Enable Power-saving mode Exit Cause exceptions */ + ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); } =20 static void spapr_cpu_destroy(PowerPCCPU *cpu) diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index d79aa44467..e720d54eb5 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -162,7 +162,6 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachi= neState *spapr, if (cpu !=3D NULL) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 if (!cs->halted) { rtas_st(rets, 0, RTAS_OUT_HW_ERROR); @@ -178,9 +177,6 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachi= neState *spapr, =20 env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); =20 - /* Enable Power-saving mode Exit Cause exceptions for the new CPU = */ - env->spr[SPR_LPCR] |=3D pcc->lpcr_pm; - spapr_cpu_set_endianness(cpu); spapr_cpu_update_tb_offset(cpu); =20 --=20 2.14.3