From nobody Mon Feb 9 20:34:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523950172535566.3698112695338; Tue, 17 Apr 2018 00:29:32 -0700 (PDT) Received: from localhost ([::1]:48299 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8L3L-0004Hr-44 for importer@patchew.org; Tue, 17 Apr 2018 03:29:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8Krv-0003TH-9D for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f8Krt-0008VW-JF for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:35 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:50869) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f8Krs-0008TP-UG; Tue, 17 Apr 2018 03:17:33 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40QGm70ycnz9s02; Tue, 17 Apr 2018 17:17:26 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1523949447; bh=kDPA2h9jL9nhIP9haLnPb2sMnFRV9qKROj1/jfvW72M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h679im/JZkxmz0w6GLqOxkOFp1QbE3uLCaltJ1l/7TLd7h85JMWqXsgw24bKtsZjl qJgAL2TbRIuS3i4MV/garUQwZsd/+spfEG0fFGT42sM8DD5eAUYIl3NIUCzH91nBlz qfgwTk0A9g4QfVCusVNbpKyvqy8qXedzDwV/p/nM= From: David Gibson To: groug@kaod.org Date: Tue, 17 Apr 2018 17:17:19 +1000 Message-Id: <20180417071722.9399-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180417071722.9399-1-david@gibson.dropbear.id.au> References: <20180417071722.9399-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PATCH for-2.13 07/10] spapr: Make a helper to set up cpu entry point state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Under PAPR, only the boot CPU is active when the system starts. Other cpus must be explicitly activated using an RTAS call. The entry state for the boot and secondary cpus isn't identical, but it has some things in common. We're going to add a bit more common setup later, too, so to simplify make a helper which sets up the common entry state for both boot and secondary cpu threads. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 4 +--- hw/ppc/spapr_cpu_core.c | 9 +++++++++ hw/ppc/spapr_rtas.c | 6 +++--- include/hw/ppc/spapr_cpu_core.h | 3 +++ 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index fbb2c6752c..e0cabfa6ee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1536,10 +1536,8 @@ static void spapr_machine_reset(void) g_free(fdt); =20 /* Set up the entry state */ - first_ppc_cpu->env.gpr[3] =3D fdt_addr; + spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr); first_ppc_cpu->env.gpr[5] =3D 0; - first_cpu->halted =3D 0; - first_ppc_cpu->env.nip =3D SPAPR_ENTRY_POINT; =20 spapr->cas_reboot =3D false; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index b1c3cf11f0..ecd40dbf03 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -80,6 +80,15 @@ static void spapr_cpu_reset(void *opaque) env->spr[SPR_AMOR] =3D 0xffffffffffffffffull; } =20 +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3) +{ + CPUPPCState *env =3D &cpu->env; + + env->nip =3D SPAPR_ENTRY_POINT; + env->gpr[3] =3D r3; + CPU(cpu)->halted =3D 0; +} + static void spapr_cpu_destroy(PowerPCCPU *cpu) { qemu_unregister_reset(spapr_cpu_reset, cpu); diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 0ec5fa4cfe..d79aa44467 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -37,6 +37,7 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_vio.h" #include "hw/ppc/spapr_rtas.h" +#include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/ppc.h" #include "hw/boards.h" =20 @@ -173,14 +174,13 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMac= hineState *spapr, * new cpu enters */ kvm_cpu_synchronize_state(cs); =20 + spapr_cpu_set_entry_state(cpu, start, r3); + env->msr =3D (1ULL << MSR_SF) | (1ULL << MSR_ME); =20 /* Enable Power-saving mode Exit Cause exceptions for the new CPU = */ env->spr[SPR_LPCR] |=3D pcc->lpcr_pm; =20 - env->nip =3D start; - env->gpr[3] =3D r3; - cs->halted =3D 0; spapr_cpu_set_endianness(cpu); spapr_cpu_update_tb_offset(cpu); =20 diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_cor= e.h index 1a38544706..11cab30838 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -12,6 +12,7 @@ #include "hw/qdev.h" #include "hw/cpu/core.h" #include "target/ppc/cpu-qom.h" +#include "target/ppc/cpu.h" =20 #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core" #define SPAPR_CPU_CORE(obj) \ @@ -40,4 +41,6 @@ typedef struct sPAPRCPUCoreClass { const char *spapr_get_cpu_core_type(const char *cpu_type); void spapr_cpu_core_reset(sPAPRCPUCore *sc); =20 +void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_u= long r3); + #endif --=20 2.14.3