From nobody Tue Feb 10 00:22:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1523949641564685.3383700979853; Tue, 17 Apr 2018 00:20:41 -0700 (PDT) Received: from localhost ([::1]:47851 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8Kuu-0005NW-Kr for importer@patchew.org; Tue, 17 Apr 2018 03:20:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57934) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f8Krt-0003Rc-DH for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f8Krq-0008Sk-8q for qemu-devel@nongnu.org; Tue, 17 Apr 2018 03:17:33 -0400 Received: from ozlabs.org ([203.11.71.1]:33081) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f8Krp-0008OO-Ki; Tue, 17 Apr 2018 03:17:30 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 40QGm63M9vz9s1p; Tue, 17 Apr 2018 17:17:26 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1523949446; bh=hYhCgNx3xUu4shxn3G6S16YVvev3rZHRn1A6Vhx37cw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Z0bH3vkoIZM9sJWjosbWVyoHazt8ZgYVNbzcLhgMgPeLdHl4GL3U4GxNW4XDamVfL cJPIPQgmG6Ya2kuBEOegPHbPqowdkOHv0Ho0Pg19jGLc11Pqe7q1emx0BHlMy2i8Pp uUlrDXmfaT4OiFivsxGCPRYEtrwM2mvee0/LE0no= From: David Gibson To: groug@kaod.org Date: Tue, 17 Apr 2018 17:17:17 +1000 Message-Id: <20180417071722.9399-6-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180417071722.9399-1-david@gibson.dropbear.id.au> References: <20180417071722.9399-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 Subject: [Qemu-devel] [PATCH for-2.13 05/10] spapr: Move PAPR mode register initialization to spapr code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" cpu_ppc_set_papr() has code to make sure the LPCR and AMOR (hypervisor privileged registers) have values which will make TCG behave correctly for paravirtualized guests, where we don't emulate the cpu when in hypervisor mode. It does this by mangling the default values of the SPRs, so that they will be set correctly at reset time. Manipulating usually-static parameters of the cpu model like this is kind of ugly, especially since the values used really have more to do with the platform than the cpu. The spapr code already has places for PAPR specific initializations of register state, so move the handling of LPCR and AMOR to there. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr_cpu_core.c | 36 +++++++++++++++++++++++++++++++++++- target/ppc/translate_init.c | 39 --------------------------------------- 2 files changed, 35 insertions(+), 40 deletions(-) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 2aab6ccd15..9080664ec1 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -28,6 +28,7 @@ static void spapr_cpu_reset(void *opaque) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong lpcr; =20 cpu_reset(cs); =20 @@ -41,13 +42,46 @@ static void spapr_cpu_reset(void *opaque) * using an RTAS call */ cs->halted =3D 1; =20 + lpcr =3D env->spr[SPR_LPCR]; + + /* Set emulated LPCR to not send interrupts to hypervisor. Note that + * under KVM, the actual HW LPCR will be set differently by KVM itself, + * the settings below ensure proper operations with TCG in absence of + * a real hypervisor. + * + * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for + * real mode accesses, which thankfully defaults to 0 and isn't + * accessible in guest mode. + */ + lpcr &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV); + lpcr |=3D LPCR_LPES0 | LPCR_LPES1; + + /* Set RMLS to the max (ie, 16G) */ + lpcr &=3D ~LPCR_RMLS; + lpcr |=3D 1ull << LPCR_RMLS_SHIFT; + + /* Only enable Power-saving mode Exit Cause exceptions on the boot + * CPU. The RTAS command start-cpu will enable them on secondaries. + */ + if (cs =3D=3D first_cpu) { + lpcr |=3D pcc->lpcr_pm; + } + /* Disable Power-saving mode Exit Cause exceptions for the CPU. * This can cause issues when rebooting the guest if a secondary * is awaken */ if (cs !=3D first_cpu) { - env->spr[SPR_LPCR] &=3D ~pcc->lpcr_pm; + lpcr &=3D ~pcc->lpcr_pm; } =20 + env->spr[SPR_LPCR] =3D lpcr; + + /* Set a full AMOR so guest can use the AMR as it sees fit */ + env->spr[SPR_AMOR] =3D 0xffffffffffffffffull; + + /* Update some env bits based on new LPCR value */ + ppc_hash64_update_rmls(cpu); + ppc_hash64_update_vrma(cpu); } =20 static void spapr_cpu_destroy(PowerPCCPU *cpu) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 14f346f441..5e89901149 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8866,11 +8866,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) #if !defined(CONFIG_USER_ONLY) void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) { - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; - ppc_spr_t *lpcr =3D &env->spr_cb[SPR_LPCR]; - ppc_spr_t *amor =3D &env->spr_cb[SPR_AMOR]; - CPUState *cs =3D CPU(cpu); =20 cpu->vhyp =3D vhyp; =20 @@ -8881,41 +8877,6 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHyp= ervisor *vhyp) */ env->msr_mask &=3D ~((1ull << MSR_EP) | MSR_HVB); =20 - /* Set emulated LPCR to not send interrupts to hypervisor. Note that - * under KVM, the actual HW LPCR will be set differently by KVM itself, - * the settings below ensure proper operations with TCG in absence of - * a real hypervisor. - * - * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for - * real mode accesses, which thankfully defaults to 0 and isn't - * accessible in guest mode. - */ - lpcr->default_value &=3D ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV= ); - lpcr->default_value |=3D LPCR_LPES0 | LPCR_LPES1; - - /* Set RMLS to the max (ie, 16G) */ - lpcr->default_value &=3D ~LPCR_RMLS; - lpcr->default_value |=3D 1ull << LPCR_RMLS_SHIFT; - - /* Only enable Power-saving mode Exit Cause exceptions on the boot - * CPU. The RTAS command start-cpu will enable them on secondaries. - */ - if (cs =3D=3D first_cpu) { - lpcr->default_value |=3D pcc->lpcr_pm; - } - - /* We should be followed by a CPU reset but update the active value - * just in case... - */ - env->spr[SPR_LPCR] =3D lpcr->default_value; - - /* Set a full AMOR so guest can use the AMR as it sees fit */ - env->spr[SPR_AMOR] =3D amor->default_value =3D 0xffffffffffffffffull; - - /* Update some env bits based on new LPCR value */ - ppc_hash64_update_rmls(cpu); - ppc_hash64_update_vrma(cpu); - /* Tell KVM that we're in PAPR mode */ if (kvm_enabled()) { kvmppc_set_papr(cpu); --=20 2.14.3