From nobody Tue Feb 10 19:15:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1522091930526902.3872716068443; Mon, 26 Mar 2018 12:18:50 -0700 (PDT) Received: from localhost ([::1]:58644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xdg-0004TD-Cl for importer@patchew.org; Mon, 26 Mar 2018 15:18:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f0Xbe-0003Cm-CT for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f0Xbc-0001OL-Vl for qemu-devel@nongnu.org; Mon, 26 Mar 2018 15:16:34 -0400 Received: from mout.kundenserver.de ([212.227.126.135]:56185) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f0Xbc-0001Mi-Kq; Mon, 26 Mar 2018 15:16:32 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue006 [212.227.15.167]) with ESMTPSA (Nemesis) id 0M47EN-1ejHdP1w3f-00rpMQ; Mon, 26 Mar 2018 21:16:20 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Mon, 26 Mar 2018 21:15:47 +0200 Message-Id: <20180326191603.10217-4-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180326191603.10217-1-laurent@vivier.eu> References: <20180326191603.10217-1-laurent@vivier.eu> X-Provags-ID: V03:K0:JS1HHyhuTgiaYS30sJHt+D98Ff8qI9nkauIVRpDrTZoUlGjEwJh lsChkROW8ZtoRXHP0iQqKidyeb8n5v7DmqrHHeEywqTvOe7YwP9ZhRbtIzatkqLg+j114hS yuRHah25ER/lkWjO7++klFIgsKkCHwGxo828s6J+bQ6R0PO9ocUAleuvfAZGhLB5va2eXS9 6luhqdqclQsPj8rsjMSLg== X-UI-Out-Filterresults: notjunk:1;V01:K0:1Cr4rlUCe1I=:Mt2Sorb4dRyQxxuBN4dDse +gWxqL6366lKfEm0bH7RQJ4b1IM++6pFkqQ1ul1bn/jj6CvOR1Gk1U3RiwbFA4y8aPIal4aPq IXlfFjl5XxQhPBW51btFTznmQQH3cYtl2D2OoN0supnVygI49woSwIs9yd12h8dCzxCrxi9Tj OZi0n9BT7iR5GOz69PVmNnKYteRe8pd4p9r3/3bWK26zsew0LmbgIOLUHPnZG7HAiw1RZjaWD nZFtDPvG+jWorNthq3fJsz7ALDMY64iIzdnNLmkNmUbM36+/CBVpRDd1rfYkB1VvZOX5zLmAm 0DrygZoCa0pOOhvd/SAJQzz1FMU4V5uAbpyN6k34XJ/++bWSRQC5VLQkNGfAfGnOpk3Z41qbl N2qQ+r3grNHy4celtisxURVOn1jhqrjuK4A+hYdG2McLNtNYyjgVgw6FNBqDs23pfm2qmuLX0 IG1z1rv/hWTIO47LHrCymWrz1Wmi6VLMc2HVHJ9YuFpwsOJ2AXxYoELNmsEK65su7LrmVghS9 cphdNkCCEqEg61xHPIISoH6Y+SfG9967ocH80DWzBJbSgCr1GrdDUxme6QDhceMbN7MVBXSWy ofnkuMhsWUTk4fhJtxujEA4Zp+zwNpBWH6BtmBQXnir5HT88MdOEhr1clikztDvEP5xShhm/Z ewWFyBeqhKzUlNmZDfJsb0lj2eI2hIrvCQ1wqIpAL07R7LW4s4/V05dkgTn86GHIH0aHzhsQq U+dBvrZfSsVOZlJJQj6W6O4LrDRTyFL5DpcBmQ== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.135 Subject: [Qemu-devel] [PATCH for 2.13 03/19] linux-user: move aarch64 cpu loop to aarch64 directory X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Riku Voipio , Cornelia Huck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No code change, only move code from main.c to aarch64/cpu_loop.c and duplicate some macro defined for both arm and aarch64. Signed-off-by: Laurent Vivier --- linux-user/aarch64/cpu_loop.c | 156 ++++++++++++++++++++++++++++++++++++++= ++++ linux-user/main.c | 109 +---------------------------- 2 files changed, 158 insertions(+), 107 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index b7700a5561..c97a646546 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -21,6 +21,162 @@ #include "qemu.h" #include "cpu_loop-common.h" =20 +#define get_user_code_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_code_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && bswap_code(arm_sctlr_b(env))) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define get_user_data_u32(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap32(x); \ + } \ + __r; \ + }) + +#define get_user_data_u16(x, gaddr, env) \ + ({ abi_long __r =3D get_user_u16((x), (gaddr)); \ + if (!__r && arm_cpu_bswap_data(env)) { \ + (x) =3D bswap16(x); \ + } \ + __r; \ + }) + +#define put_user_data_u32(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap32(__x); \ + } \ + put_user_u32(__x, (gaddr)); \ + }) + +#define put_user_data_u16(x, gaddr, env) \ + ({ typeof(x) __x =3D (x); \ + if (arm_cpu_bswap_data(env)) { \ + __x =3D bswap16(__x); \ + } \ + put_user_u16(__x, (gaddr)); \ + }) + +/* AArch64 main loop */ +void cpu_loop(CPUARMState *env) +{ + CPUState *cs =3D CPU(arm_env_get_cpu(env)); + int trapnr, sig; + abi_long ret; + target_siginfo_t info; + + for (;;) { + cpu_exec_start(cs); + trapnr =3D cpu_exec(cs); + cpu_exec_end(cs); + process_queued_cpu_work(cs); + + switch (trapnr) { + case EXCP_SWI: + ret =3D do_syscall(env, + env->xregs[8], + env->xregs[0], + env->xregs[1], + env->xregs[2], + env->xregs[3], + env->xregs[4], + env->xregs[5], + 0, 0); + if (ret =3D=3D -TARGET_ERESTARTSYS) { + env->pc -=3D 4; + } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { + env->xregs[0] =3D ret; + } + break; + case EXCP_INTERRUPT: + /* just indicate that signals should be handled asap */ + break; + case EXCP_UDEF: + info.si_signo =3D TARGET_SIGILL; + info.si_errno =3D 0; + info.si_code =3D TARGET_ILL_ILLOPN; + info._sifields._sigfault._addr =3D env->pc; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + /* XXX: check env->error_code */ + info.si_code =3D TARGET_SEGV_MAPERR; + info._sifields._sigfault._addr =3D env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + case EXCP_DEBUG: + case EXCP_BKPT: + sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); + if (sig) { + info.si_signo =3D sig; + info.si_errno =3D 0; + info.si_code =3D TARGET_TRAP_BRKPT; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + } + break; + case EXCP_SEMIHOST: + env->xregs[0] =3D do_arm_semihosting(env); + break; + case EXCP_YIELD: + /* nothing to do here for user-mode, just resume guest code */ + break; + case EXCP_ATOMIC: + cpu_exec_step_atomic(cs); + break; + default: + EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); + abort(); + } + process_pending_signals(env); + /* Exception return on AArch64 always clears the exclusive monitor, + * so any return to running guest code implies this. + */ + env->exclusive_addr =3D -1; + } +} + void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { + CPUState *cpu =3D ENV_GET_CPU(env); + TaskState *ts =3D cpu->opaque; + struct image_info *info =3D ts->info; + int i; + + if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { + fprintf(stderr, + "The selected ARM CPU does not support 64 bit mode\n"); + exit(EXIT_FAILURE); + } + + for (i =3D 0; i < 31; i++) { + env->xregs[i] =3D regs->regs[i]; + } + env->pc =3D regs->pc; + env->xregs[31] =3D regs->sp; +#ifdef TARGET_WORDS_BIGENDIAN + env->cp15.sctlr_el[1] |=3D SCTLR_E0E; + for (i =3D 1; i < 4; ++i) { + env->cp15.sctlr_el[i] |=3D SCTLR_EE; + } +#endif + + ts->stack_base =3D info->start_stack; + ts->heap_base =3D info->brk; + /* This will be filled in on the first SYS_HEAPINFO call. */ + ts->heap_limit =3D 0; } diff --git a/linux-user/main.c b/linux-user/main.c index 0b792024ce..40be5cf201 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -555,89 +555,6 @@ void cpu_loop(CPUARMState *env) process_pending_signals(env); } } - -#else - -/* AArch64 main loop */ -void cpu_loop(CPUARMState *env) -{ - CPUState *cs =3D CPU(arm_env_get_cpu(env)); - int trapnr, sig; - abi_long ret; - target_siginfo_t info; - - for (;;) { - cpu_exec_start(cs); - trapnr =3D cpu_exec(cs); - cpu_exec_end(cs); - process_queued_cpu_work(cs); - - switch (trapnr) { - case EXCP_SWI: - ret =3D do_syscall(env, - env->xregs[8], - env->xregs[0], - env->xregs[1], - env->xregs[2], - env->xregs[3], - env->xregs[4], - env->xregs[5], - 0, 0); - if (ret =3D=3D -TARGET_ERESTARTSYS) { - env->pc -=3D 4; - } else if (ret !=3D -TARGET_QEMU_ESIGRETURN) { - env->xregs[0] =3D ret; - } - break; - case EXCP_INTERRUPT: - /* just indicate that signals should be handled asap */ - break; - case EXCP_UDEF: - info.si_signo =3D TARGET_SIGILL; - info.si_errno =3D 0; - info.si_code =3D TARGET_ILL_ILLOPN; - info._sifields._sigfault._addr =3D env->pc; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ - info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->exception.vaddress; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - break; - case EXCP_DEBUG: - case EXCP_BKPT: - sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) { - info.si_signo =3D sig; - info.si_errno =3D 0; - info.si_code =3D TARGET_TRAP_BRKPT; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } - break; - case EXCP_SEMIHOST: - env->xregs[0] =3D do_arm_semihosting(env); - break; - case EXCP_YIELD: - /* nothing to do here for user-mode, just resume guest code */ - break; - case EXCP_ATOMIC: - cpu_exec_step_atomic(cs); - break; - default: - EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\= n", trapnr); - abort(); - } - process_pending_signals(env); - /* Exception return on AArch64 always clears the exclusive monitor, - * so any return to running guest code implies this. - */ - env->exclusive_addr =3D -1; - } -} #endif /* ndef TARGET_ABI32 */ =20 #endif @@ -4492,29 +4409,7 @@ int main(int argc, char **argv, char **envp) =20 target_cpu_copy_regs(env, regs); =20 -#if defined(TARGET_AARCH64) - { - int i; - - if (!(arm_feature(env, ARM_FEATURE_AARCH64))) { - fprintf(stderr, - "The selected ARM CPU does not support 64 bit mode\n"); - exit(EXIT_FAILURE); - } - - for (i =3D 0; i < 31; i++) { - env->xregs[i] =3D regs->regs[i]; - } - env->pc =3D regs->pc; - env->xregs[31] =3D regs->sp; -#ifdef TARGET_WORDS_BIGENDIAN - env->cp15.sctlr_el[1] |=3D SCTLR_E0E; - for (i =3D 1; i < 4; ++i) { - env->cp15.sctlr_el[i] |=3D SCTLR_EE; - } -#endif - } -#elif defined(TARGET_ARM) +#if defined(TARGET_ARM) && !defined(TARGET_AARCH64) { int i; cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC, @@ -4769,7 +4664,7 @@ int main(int argc, char **argv, char **envp) } #endif =20 -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if (defined(TARGET_ARM) && !defined(TARGET_AARCH64)) || defined(TARGET_M6= 8K) ts->stack_base =3D info->start_stack; ts->heap_base =3D info->brk; /* This will be filled in on the first SYS_HEAPINFO call. */ --=20 2.14.3