From nobody Sun Oct 26 07:43:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521537121918138.24484848769498; Tue, 20 Mar 2018 02:12:01 -0700 (PDT) Received: from localhost ([::1]:46933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyDJJ-0005Ay-1L for importer@patchew.org; Tue, 20 Mar 2018 05:12:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eyDFs-00032v-G4 for qemu-devel@nongnu.org; Tue, 20 Mar 2018 05:08:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eyDFn-0002OW-DB for qemu-devel@nongnu.org; Tue, 20 Mar 2018 05:08:28 -0400 Received: from mout.kundenserver.de ([212.227.126.134]:40511) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eyDFn-0002N9-25 for qemu-devel@nongnu.org; Tue, 20 Mar 2018 05:08:23 -0400 Received: from localhost.localdomain ([78.238.229.36]) by mrelayeu.kundenserver.de (mreue002 [212.227.15.167]) with ESMTPSA (Nemesis) id 0ME6mN-1epAqo0sIB-00HOex; Tue, 20 Mar 2018 10:08:21 +0100 From: Laurent Vivier To: qemu-devel@nongnu.org Date: Tue, 20 Mar 2018 10:08:12 +0100 Message-Id: <20180320090813.852-2-laurent@vivier.eu> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180320090813.852-1-laurent@vivier.eu> References: <20180320090813.852-1-laurent@vivier.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K0:8qozlPS/bS41REdc7JtPfTmN5M58MPn6jI9nBSopk7c/jz1JIbx l2jFVfR3RMD0g1xmRTjWVMYWVN+YkB2p/wSvONJ+dT/JXM2JCVtS+iXxVcFOizi/+zUl6d6 ZfGy3uI78yZPV14TlMFnblm4LjCVL65Ge3UEXGITmmirEETFSBOCO0wcAnpbCacbRXfkgOm g7KQXvqIFv8UgcXWXmbmw== X-UI-Out-Filterresults: notjunk:1;V01:K0:4j/JdLTZ9eI=:/28Qzb5S3WfPGD6Oe7OMoD xe81qrFb9nyIRKgKYEWDcM+OUGX9Vh4nUfErfJ2+xxehOgQLEceGN2b9P1hFJImW6g/zJOlXc HJVjtv6YMnvxR+o6cIDZLNjSBSNhCi+1pquiFRmZetENgK4Wr2Rm34GWAP7HR1RIrEx0fmK/7 oO2ScsBsrUswHuEiui9nwXOML3aBLP7yJjyXQaLaCtorN5qyUnYm3K6hA6pFKVu+hntk/7s4b lO9pFA4vdCyg+Ev9cL92avTMVhNf6Ys8jJkcvKLo0l/BGWOovYkMhjP+wQLqMRb8+cyyCoVCE JMy14dJ7YiZ1WiKJB97w3cEPvmS755wByxRQ88QIiN1wfnTek05qnzUe5Y3GHz5NaqlHxhmYV 18H7qTPPG3QspVdTSTbcDlSanOigAxiu4ajv4HsHAqJHMOCw3ZdPsG1sourJQaaXJW8jr9/FI Htmj2cVGOb5GrqKc+/r2tpnuCH+xo8DuewhM0rNglEprg5kQgrPWZ9tHAq+xLmG9jzdmXqUfu 4j30NFNG8k2gnQovjEjcrVpngt9zUOyuWFbdgjv9oOV4eutB8pcO127L4iE0LLhL0xARClesE NhedRZNjHfDnsG6vwIByR5ScEpLb7CNBY4aEfbXqZBis1Rz/IOhqpwarcFRojJQVqQCHTLr9u EDQ+SSO+Sz5agkh16sc6X7nNlTB4dVOtBhtGOcJkcCJyI3cqmDVh5Lxgtx21je67Xc6H116IY ZE2HKDtGC5DmaRjU3U9KRy3Die+LPmpZT63QR2enqTNQ9H5SFnZZqyzyRdQ= X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 212.227.126.134 Subject: [Qemu-devel] [PULL 1/2] target/m68k: add DisasContext parameter to gen_extend() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 This parameter will be needed to manage automatic release of temporary allocated TCG variables. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20180319113544.704-2-laurent@vivier.eu> --- target/m68k/translate.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index cef6f663ad..1c2ff56305 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -617,7 +617,7 @@ static void gen_flush_flags(DisasContext *s) s->cc_op =3D CC_OP_FLAGS; } =20 -static inline TCGv gen_extend(TCGv val, int opsize, int sign) +static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int s= ign) { TCGv tmp; =20 @@ -811,7 +811,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, gen_partset_reg(opsize, reg, val); return store_dummy; } else { - return gen_extend(reg, opsize, what =3D=3D EA_LOADS); + return gen_extend(s, reg, opsize, what =3D=3D EA_LOADS); } case 1: /* Address register direct. */ reg =3D get_areg(s, reg0); @@ -819,7 +819,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, tcg_gen_mov_i32(reg, val); return store_dummy; } else { - return gen_extend(reg, opsize, what =3D=3D EA_LOADS); + return gen_extend(s, reg, opsize, what =3D=3D EA_LOADS); } case 2: /* Indirect register */ reg =3D get_areg(s, reg0); @@ -1759,8 +1759,8 @@ DISAS_INSN(abcd_reg) =20 gen_flush_flags(s); /* !Z is sticky */ =20 - src =3D gen_extend(DREG(insn, 0), OS_BYTE, 0); - dest =3D gen_extend(DREG(insn, 9), OS_BYTE, 0); + src =3D gen_extend(s, DREG(insn, 0), OS_BYTE, 0); + dest =3D gen_extend(s, DREG(insn, 9), OS_BYTE, 0); bcd_add(dest, src); gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); =20 @@ -1794,8 +1794,8 @@ DISAS_INSN(sbcd_reg) =20 gen_flush_flags(s); /* !Z is sticky */ =20 - src =3D gen_extend(DREG(insn, 0), OS_BYTE, 0); - dest =3D gen_extend(DREG(insn, 9), OS_BYTE, 0); + src =3D gen_extend(s, DREG(insn, 0), OS_BYTE, 0); + dest =3D gen_extend(s, DREG(insn, 9), OS_BYTE, 0); =20 bcd_sub(dest, src); =20 @@ -1856,7 +1856,7 @@ DISAS_INSN(addsub) =20 add =3D (insn & 0x4000) !=3D 0; opsize =3D insn_opsize(insn); - reg =3D gen_extend(DREG(insn, 9), opsize, 1); + reg =3D gen_extend(s, DREG(insn, 9), opsize, 1); dest =3D tcg_temp_new(); if (insn & 0x100) { SRC_EA(env, tmp, opsize, 1, &addr); @@ -2386,7 +2386,7 @@ DISAS_INSN(cas) return; } =20 - cmp =3D gen_extend(DREG(ext, 0), opsize, 1); + cmp =3D gen_extend(s, DREG(ext, 0), opsize, 1); =20 /* if =3D=3D Dc then * =3D Du @@ -3055,7 +3055,7 @@ DISAS_INSN(or) int opsize; =20 opsize =3D insn_opsize(insn); - reg =3D gen_extend(DREG(insn, 9), opsize, 0); + reg =3D gen_extend(s, DREG(insn, 9), opsize, 0); dest =3D tcg_temp_new(); if (insn & 0x100) { SRC_EA(env, src, opsize, 0, &addr); @@ -3120,8 +3120,8 @@ DISAS_INSN(subx_reg) =20 opsize =3D insn_opsize(insn); =20 - src =3D gen_extend(DREG(insn, 0), opsize, 1); - dest =3D gen_extend(DREG(insn, 9), opsize, 1); + src =3D gen_extend(s, DREG(insn, 0), opsize, 1); + dest =3D gen_extend(s, DREG(insn, 9), opsize, 1); =20 gen_subx(s, src, dest, opsize); =20 @@ -3176,7 +3176,7 @@ DISAS_INSN(cmp) =20 opsize =3D insn_opsize(insn); SRC_EA(env, src, opsize, 1, NULL); - reg =3D gen_extend(DREG(insn, 9), opsize, 1); + reg =3D gen_extend(s, DREG(insn, 9), opsize, 1); gen_update_cc_cmp(s, reg, src, opsize); } =20 @@ -3329,8 +3329,8 @@ DISAS_INSN(addx_reg) =20 opsize =3D insn_opsize(insn); =20 - dest =3D gen_extend(DREG(insn, 9), opsize, 1); - src =3D gen_extend(DREG(insn, 0), opsize, 1); + dest =3D gen_extend(s, DREG(insn, 9), opsize, 1); + src =3D gen_extend(s, DREG(insn, 0), opsize, 1); =20 gen_addx(s, src, dest, opsize); =20 @@ -3369,7 +3369,7 @@ static inline void shift_im(DisasContext *s, uint16_t= insn, int opsize) int logical =3D insn & 8; int left =3D insn & 0x100; int bits =3D opsize_bytes(opsize) * 8; - TCGv reg =3D gen_extend(DREG(insn, 0), opsize, !logical); + TCGv reg =3D gen_extend(s, DREG(insn, 0), opsize, !logical); =20 if (count =3D=3D 0) { count =3D 8; @@ -3419,7 +3419,7 @@ static inline void shift_reg(DisasContext *s, uint16_= t insn, int opsize) int logical =3D insn & 8; int left =3D insn & 0x100; int bits =3D opsize_bytes(opsize) * 8; - TCGv reg =3D gen_extend(DREG(insn, 0), opsize, !logical); + TCGv reg =3D gen_extend(s, DREG(insn, 0), opsize, !logical); TCGv s32; TCGv_i64 t64, s64; =20 @@ -3556,7 +3556,7 @@ DISAS_INSN(shift_mem) while M68000 sets if the most significant bit is changed at any time during the shift operation */ if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { - src =3D gen_extend(src, OS_WORD, 1); + src =3D gen_extend(s, src, OS_WORD, 1); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); } } else { @@ -3789,7 +3789,7 @@ DISAS_INSN(rotate8_im) TCGv shift; int tmp; =20 - reg =3D gen_extend(DREG(insn, 0), OS_BYTE, 0); + reg =3D gen_extend(s, DREG(insn, 0), OS_BYTE, 0); =20 tmp =3D (insn >> 9) & 7; if (tmp =3D=3D 0) { @@ -3816,7 +3816,7 @@ DISAS_INSN(rotate16_im) TCGv shift; int tmp; =20 - reg =3D gen_extend(DREG(insn, 0), OS_WORD, 0); + reg =3D gen_extend(s, DREG(insn, 0), OS_WORD, 0); tmp =3D (insn >> 9) & 7; if (tmp =3D=3D 0) { tmp =3D 8; @@ -3876,7 +3876,7 @@ DISAS_INSN(rotate8_reg) TCGv t0, t1; int left =3D (insn & 0x100); =20 - reg =3D gen_extend(DREG(insn, 0), OS_BYTE, 0); + reg =3D gen_extend(s, DREG(insn, 0), OS_BYTE, 0); src =3D DREG(insn, 9); /* shift in [0..63] */ t0 =3D tcg_temp_new_i32(); @@ -3911,7 +3911,7 @@ DISAS_INSN(rotate16_reg) TCGv t0, t1; int left =3D (insn & 0x100); =20 - reg =3D gen_extend(DREG(insn, 0), OS_WORD, 0); + reg =3D gen_extend(s, DREG(insn, 0), OS_WORD, 0); src =3D DREG(insn, 9); /* shift in [0..63] */ t0 =3D tcg_temp_new_i32(); @@ -4353,7 +4353,7 @@ DISAS_INSN(chk) return; } SRC_EA(env, src, opsize, 1, NULL); - reg =3D gen_extend(DREG(insn, 9), opsize, 1); + reg =3D gen_extend(s, DREG(insn, 9), opsize, 1); =20 gen_flush_flags(s); gen_helper_chk(cpu_env, reg, src); --=20 2.14.3