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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Mon, 19 Mar 2018 18:34:06 +0000
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Subject: [Qemu-devel] [PULL 04/13] char: i.MX: Add support for "TX complete"
interrupt
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From: Andrey Smirnov <andrew.smirnov@gmail.com>
Add support for "TX complete"/TXDC interrupt generate by real HW since
it is needed to support guests other than Linux.
Based on the patch by Bill Paul as found here:
https://bugs.launchpad.net/qemu/+bug/1753314
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: Bill Paul <wpaul@windriver.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bill Paul <wpaul@windriver.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Message-id: 20180315191141.6789-2-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/char/imx_serial.h | 3 +++
hw/char/imx_serial.c | 20 +++++++++++++++++---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index baeec3183f..5b99cee7cf 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -67,6 +67,8 @@
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
=20
+#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
+
#define UTS1_TXEMPTY (1<<6)
#define UTS1_RXEMPTY (1<<5)
#define UTS1_TXFULL (1<<4)
@@ -95,6 +97,7 @@ typedef struct IMXSerialState {
uint32_t ubmr;
uint32_t ubrc;
uint32_t ucr3;
+ uint32_t ucr4;
=20
qemu_irq irq;
CharBackend chr;
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index d1e8586280..1e5540472b 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -37,8 +37,8 @@
=20
static const VMStateDescription vmstate_imx_serial =3D {
.name =3D TYPE_IMX_SERIAL,
- .version_id =3D 1,
- .minimum_version_id =3D 1,
+ .version_id =3D 2,
+ .minimum_version_id =3D 2,
.fields =3D (VMStateField[]) {
VMSTATE_INT32(readbuff, IMXSerialState),
VMSTATE_UINT32(usr1, IMXSerialState),
@@ -50,6 +50,7 @@ static const VMStateDescription vmstate_imx_serial =3D {
VMSTATE_UINT32(ubmr, IMXSerialState),
VMSTATE_UINT32(ubrc, IMXSerialState),
VMSTATE_UINT32(ucr3, IMXSerialState),
+ VMSTATE_UINT32(ucr4, IMXSerialState),
VMSTATE_END_OF_LIST()
},
};
@@ -71,6 +72,11 @@ static void imx_update(IMXSerialState *s)
* unfortunately.
*/
mask =3D (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
+ /*
+ * TCEN and TXDC are both bit 3
+ */
+ mask |=3D s->ucr4 & UCR4_TCEN;
+
usr2 =3D s->usr2 & mask;
=20
qemu_set_irq(s->irq, usr1 || usr2);
@@ -163,6 +169,8 @@ static uint64_t imx_serial_read(void *opaque, hwaddr of=
fset,
return s->ucr3;
=20
case 0x23: /* UCR4 */
+ return s->ucr4;
+
case 0x29: /* BRM Incremental */
return 0x0; /* TODO */
=20
@@ -191,8 +199,10 @@ static void imx_serial_write(void *opaque, hwaddr offs=
et,
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
s->usr1 &=3D ~USR1_TRDY;
+ s->usr2 &=3D ~USR2_TXDC;
imx_update(s);
s->usr1 |=3D USR1_TRDY;
+ s->usr2 |=3D USR2_TXDC;
imx_update(s);
}
break;
@@ -265,8 +275,12 @@ static void imx_serial_write(void *opaque, hwaddr offs=
et,
s->ucr3 =3D value & 0xffff;
break;
=20
- case 0x2d: /* UTS1 */
case 0x23: /* UCR4 */
+ s->ucr4 =3D value & 0xffff;
+ imx_update(s);
+ break;
+
+ case 0x2d: /* UTS1 */
qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
/* TODO */
--=20
2.16.2