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X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PULL v2 2/3] tcg/i386: Support INDEX_op_dup2_vec for -m32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Unknown why -m32 was passing with gcc but not clang; it should have failed for both. This would be used for tcg_gen_dup_i64_vec, and visible with the right TB and an aarch64 guest. Reported-by: Max Reitz Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fc05909d1d..d7e59e79c5 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, case INDEX_op_x86_packus_vec: insn =3D packus_insn[vece]; goto gen_simd; +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_dup2_vec: + /* Constraints have already placed both 32-bit inputs in xmm regs.= */ + insn =3D OPC_PUNPCKLDQ; + goto gen_simd; +#endif gen_simd: tcg_debug_assert(insn !=3D OPC_UD2); if (type =3D=3D TCG_TYPE_V256) { @@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_x86_vperm2i128_vec: case INDEX_op_x86_punpckl_vec: case INDEX_op_x86_punpckh_vec: +#if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_dup2_vec: +#endif return &x_x_x; case INDEX_op_dup_vec: case INDEX_op_shli_vec: --=20 2.14.3