From nobody Sat Oct 25 02:31:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1521127035770445.8312229793163; Thu, 15 Mar 2018 08:17:15 -0700 (PDT) Received: from localhost ([::1]:52092 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewUd0-0005s0-Qh for importer@patchew.org; Thu, 15 Mar 2018 11:17:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49086) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ewUbs-0005WW-Ln for qemu-devel@nongnu.org; Thu, 15 Mar 2018 11:16:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ewUbo-0001gw-KR for qemu-devel@nongnu.org; Thu, 15 Mar 2018 11:16:04 -0400 Received: from 9pmail.ess.barracuda.com ([64.235.154.210]:54708) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ewUbo-0001K5-4G for qemu-devel@nongnu.org; Thu, 15 Mar 2018 11:16:00 -0400 Received: from mipsdag02.mipstec.com (mail2.mips.com [12.201.5.32]) by mx1402.ess.rzc.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO); Thu, 15 Mar 2018 15:14:29 +0000 Received: from LDT-J-COWGILL.mipstec.com (192.168.155.34) by mipsdag02.mipstec.com (10.20.40.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1415.2; Thu, 15 Mar 2018 08:14:30 -0700 From: James Cowgill To: , Riku Voipio , Laurent Vivier Date: Thu, 15 Mar 2018 15:13:48 +0000 Message-ID: <20180315151348.6451-1-james.cowgill@mips.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180314153121.23838-1-james.cowgill@mips.com> References: <20180314153121.23838-1-james.cowgill@mips.com> MIME-Version: 1.0 X-Originating-IP: [192.168.155.34] X-ClientProxiedBy: mipsdag02.mipstec.com (10.20.40.47) To mipsdag02.mipstec.com (10.20.40.47) X-BESS-ID: 1521126867-321458-3580-2817-1 X-BESS-VER: 2018.2-r1803082101 X-BESS-Apparent-Source-IP: 12.201.5.32 X-BESS-BRTS-Status: 1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 64.235.154.210 Subject: [Qemu-devel] [PATCH v2] linux-user: implement HWCAP bits on MIPS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Cowgill , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the two currently defined HWCAP bits on MIPS - R6 and MSA. Buglink: https://bugs.launchpad.net/qemu/+bug/1754372 Signed-off-by: James Cowgill Reviewed-by: Laurent Vivier --- v2 changes: - Fix kernel hwcap.h path. linux-user/elfload.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5fc130cc20..318c124712 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -950,6 +950,30 @@ static void elf_core_copy_regs(target_elf_gregset_t *r= egs, const CPUMIPSState *e #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 =20 +/* See arch/mips/include/uapi/asm/hwcap.h. */ +enum { + HWCAP_MIPS_R6 =3D (1 << 0), + HWCAP_MIPS_MSA =3D (1 << 1), +}; + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + MIPSCPU *cpu =3D MIPS_CPU(thread_cpu); + uint32_t hwcaps =3D 0; + +#define GET_FEATURE(flag, hwcap) \ + do { if (cpu->env.insn_flags & (flag)) { hwcaps |=3D hwcap; } } while = (0) + + GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); + +#undef GET_FEATURE + + return hwcaps; +} + #endif /* TARGET_MIPS */ =20 #ifdef TARGET_MICROBLAZE --=20 2.16.2