From nobody Sun Feb 8 17:21:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15208849577141006.9785077465084; Mon, 12 Mar 2018 13:02:37 -0700 (PDT) Received: from localhost ([::1]:34349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evTeW-0000t0-Kj for importer@patchew.org; Mon, 12 Mar 2018 16:02:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evTcY-0008J7-55 for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evTcW-000123-Vl for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44420) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evTcW-00011U-OU for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:32 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E119CC0587D2; Mon, 12 Mar 2018 20:00:31 +0000 (UTC) Received: from localhost (ovpn-116-64.gru2.redhat.com [10.97.116.64]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2EF915E1C3; Mon, 12 Mar 2018 20:00:30 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell Date: Mon, 12 Mar 2018 17:00:22 -0300 Message-Id: <20180312200022.9760-4-ehabkost@redhat.com> In-Reply-To: <20180312200022.9760-1-ehabkost@redhat.com> References: <20180312200022.9760-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Mon, 12 Mar 2018 20:00:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 3/3] i386: Add support to get/set/migrate Intel Processor Trace feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Chao Peng , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chao Peng Add Intel Processor Trace related definition. It also add corresponding part to kvm_get/set_msr and vmstate. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang Message-Id: <1520182116-16485-2-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 22 ++++++++++++++++++++++ target/i386/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/i386/machine.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ec2a771299..0c3f51445e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -415,6 +415,21 @@ typedef enum X86Seg { #define MSR_MC0_ADDR 0x402 #define MSR_MC0_MISC 0x403 =20 +#define MSR_IA32_RTIT_OUTPUT_BASE 0x560 +#define MSR_IA32_RTIT_OUTPUT_MASK 0x561 +#define MSR_IA32_RTIT_CTL 0x570 +#define MSR_IA32_RTIT_STATUS 0x571 +#define MSR_IA32_RTIT_CR3_MATCH 0x572 +#define MSR_IA32_RTIT_ADDR0_A 0x580 +#define MSR_IA32_RTIT_ADDR0_B 0x581 +#define MSR_IA32_RTIT_ADDR1_A 0x582 +#define MSR_IA32_RTIT_ADDR1_B 0x583 +#define MSR_IA32_RTIT_ADDR2_A 0x584 +#define MSR_IA32_RTIT_ADDR2_B 0x585 +#define MSR_IA32_RTIT_ADDR3_A 0x586 +#define MSR_IA32_RTIT_ADDR3_B 0x587 +#define MAX_RTIT_ADDRS 8 + #define MSR_EFER 0xc0000080 =20 #define MSR_EFER_SCE (1 << 0) @@ -1157,6 +1172,13 @@ typedef struct CPUX86State { uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; =20 + uint64_t msr_rtit_ctrl; + uint64_t msr_rtit_status; + uint64_t msr_rtit_output_base; + uint64_t msr_rtit_output_mask; + uint64_t msr_rtit_cr3_match; + uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f5d3d73ed6..d996cca68b 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1815,6 +1815,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); } } + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + int addr_num =3D kvm_arch_get_supported_cpuid(kvm_state, + 0x14, 1, R_EAX) & 0x7; + + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, + env->msr_rtit_ctrl); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, + env->msr_rtit_status); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, + env->msr_rtit_output_base); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, + env->msr_rtit_output_mask); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, + env->msr_rtit_cr3_match); + for (i =3D 0; i < addr_num; i++) { + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, + env->msr_rtit_addrs[i]); + } + } =20 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ @@ -2128,6 +2147,20 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + int addr_num =3D + kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; + + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); + for (i =3D 0; i < addr_num; i++) { + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); + } + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -2368,6 +2401,24 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_SPEC_CTRL: env->spec_ctrl =3D msrs[i].data; break; + case MSR_IA32_RTIT_CTL: + env->msr_rtit_ctrl =3D msrs[i].data; + break; + case MSR_IA32_RTIT_STATUS: + env->msr_rtit_status =3D msrs[i].data; + break; + case MSR_IA32_RTIT_OUTPUT_BASE: + env->msr_rtit_output_base =3D msrs[i].data; + break; + case MSR_IA32_RTIT_OUTPUT_MASK: + env->msr_rtit_output_mask =3D msrs[i].data; + break; + case MSR_IA32_RTIT_CR3_MATCH: + env->msr_rtit_cr3_match =3D msrs[i].data; + break; + case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: + env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] =3D msrs[i]= .data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 361c05aedf..c05fe6fb1a 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -837,6 +837,43 @@ static const VMStateDescription vmstate_spec_ctrl =3D { } }; =20 +static bool intel_pt_enable_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + int i; + + if (env->msr_rtit_ctrl || env->msr_rtit_status || + env->msr_rtit_output_base || env->msr_rtit_output_mask || + env->msr_rtit_cr3_match) { + return true; + } + + for (i =3D 0; i < MAX_RTIT_ADDRS; i++) { + if (env->msr_rtit_addrs[i]) { + return true; + } + } + + return false; +} + +static const VMStateDescription vmstate_msr_intel_pt =3D { + .name =3D "cpu/intel_pt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D intel_pt_enable_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU), + VMSTATE_UINT64(env.msr_rtit_status, X86CPU), + VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU), + VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU), + VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU), + VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -957,6 +994,7 @@ VMStateDescription vmstate_x86_cpu =3D { #endif &vmstate_spec_ctrl, &vmstate_mcg_ext_ctl, + &vmstate_msr_intel_pt, NULL } }; --=20 2.14.3