From nobody Sun May 5 21:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520885054023613.9714953069165; Mon, 12 Mar 2018 13:04:14 -0700 (PDT) Received: from localhost ([::1]:34354 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evTg5-0001t8-C4 for importer@patchew.org; Mon, 12 Mar 2018 16:04:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1evTcT-0008Ft-U6 for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1evTcS-0000zM-12 for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44344) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1evTcR-0000yy-PF for qemu-devel@nongnu.org; Mon, 12 Mar 2018 16:00:27 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F33B4C0587C9; Mon, 12 Mar 2018 20:00:26 +0000 (UTC) Received: from localhost (ovpn-116-64.gru2.redhat.com [10.97.116.64]) by smtp.corp.redhat.com (Postfix) with ESMTP id EBBC217D6F; Mon, 12 Mar 2018 20:00:24 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell Date: Mon, 12 Mar 2018 17:00:20 -0300 Message-Id: <20180312200022.9760-2-ehabkost@redhat.com> In-Reply-To: <20180312200022.9760-1-ehabkost@redhat.com> References: <20180312200022.9760-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Mon, 12 Mar 2018 20:00:27 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 1/3] target-i386: add KVM_HINTS_DEDICATED performance hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= , Wanpeng Li , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Wanpeng Li Add KVM_HINTS_DEDICATED performance hint, guest checks this feature bit to determine if they run on dedicated vCPUs, allowing optimizations such as usage of qspinlocks. Cc: Paolo Bonzini Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 Cc: Eduardo Habkost Signed-off-by: Wanpeng Li Message-Id: <1518185725-69559-1-git-send-email-wanpengli@tencent.com> [ehabkost: Renamed property to kvm-hint-dedicated] Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 3 +++ target/i386/cpu.c | 14 ++++++++++++++ target/i386/kvm.c | 4 ++++ 3 files changed, 21 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index faf39ec1ce..8d977ec567 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -471,6 +471,7 @@ typedef enum FeatureWord { FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ + FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ @@ -666,6 +667,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ =20 +#define KVM_HINTS_DEDICATED (1U << 0) + #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Predicti= on Barrier */ =20 #define CPUID_XSAVE_XSAVEOPT (1U << 0) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2c04645cea..5ea1931b7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -359,6 +359,20 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS= ] =3D { .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EAX, .tcg_features =3D TCG_KVM_FEATURES, }, + [FEAT_KVM_HINTS] =3D { + .feat_names =3D { + "kvm-hint-dedicated", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid_eax =3D KVM_CPUID_FEATURES, .cpuid_reg =3D R_EDX, + .tcg_features =3D TCG_KVM_FEATURES, + }, [FEAT_HYPERV_EAX] =3D { .feat_names =3D { NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refco= unt_access */, diff --git a/target/i386/kvm.c b/target/i386/kvm.c index ad4b159b28..44ee524188 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -383,6 +383,9 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, if (!kvm_irqchip_in_kernel()) { ret &=3D ~(1U << KVM_FEATURE_PV_UNHALT); } + } else if (function =3D=3D KVM_CPUID_FEATURES && reg =3D=3D R_EDX) { + ret |=3D KVM_HINTS_DEDICATED; + found =3D 1; } =20 /* fallback for older kernels */ @@ -801,6 +804,7 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; c->function =3D KVM_CPUID_FEATURES | kvm_base; c->eax =3D env->features[FEAT_KVM]; + c->edx =3D env->features[FEAT_KVM_HINTS]; } =20 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); --=20 2.14.3 From nobody Sun May 5 21:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520885157602120.2783228008318; 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Mon, 12 Mar 2018 20:00:28 +0000 (UTC) Received: from localhost (ovpn-116-64.gru2.redhat.com [10.97.116.64]) by smtp.corp.redhat.com (Postfix) with ESMTP id 54B3E17A9B; Mon, 12 Mar 2018 20:00:28 +0000 (UTC) From: Eduardo Habkost To: Peter Maydell Date: Mon, 12 Mar 2018 17:00:21 -0300 Message-Id: <20180312200022.9760-3-ehabkost@redhat.com> In-Reply-To: <20180312200022.9760-1-ehabkost@redhat.com> References: <20180312200022.9760-1-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 12 Mar 2018 20:00:28 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 2/3] i386: Add Intel Processor Trace feature support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Chao Peng , qemu-devel@nongnu.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Chao Peng Expose Intel Processor Trace feature to guest. To make Intel PT live migration safe and get same CPUID information with same CPU model on diffrent host. CPUID[14] is constant in this patch. Intel PT use EPT is first supported in IceLake, the CPUID[14] get on this machine as default value. Intel PT would be disabled if any machine don't support this minial feature list. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang Message-Id: <1520182116-16485-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 1 + target/i386/cpu.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++-- target/i386/kvm.c | 23 ++++++++++++++++ 3 files changed, 100 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8d977ec567..ec2a771299 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -641,6 +641,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimize= d */ #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ +#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Recip= rocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5ea1931b7e..ec1efd3a3c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -173,7 +173,32 @@ #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 =20 - +/* CPUID Leaf 0x14 constants: */ +#define INTEL_PT_MAX_SUBLEAF 0x1 +/* + * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MAT= CH + * MSR can be accessed; + * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; + * bit[02]: Support IP Filtering, TraceStop filtering, and preservation + * of Intel PT MSRs across warm reset; + * bit[03]: Support MTC timing packet and suppression of COFI-based packet= s; + */ +#define INTEL_PT_MINIMAL_EBX 0xf +/* + * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA =3D 1 and + * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can = be + * accessed; + * bit[01]: ToPA tables can hold any number of output entries, up to the + * maximum allowed by the MaskOrTableOffset field of + * IA32_RTIT_OUTPUT_MASK_PTRS; + * bit[02]: Support Single-Range Output scheme; + */ +#define INTEL_PT_MINIMAL_ECX 0x7 +#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ran= ges */ +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 +#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ +#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ +#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) @@ -442,7 +467,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { NULL, NULL, "mpx", NULL, "avx512f", "avx512dq", "rdseed", "adx", "smap", "avx512ifma", "pcommit", "clflushopt", - "clwb", NULL, "avx512pf", "avx512er", + "clwb", "intel-pt", "avx512pf", "avx512er", "avx512cd", "sha-ni", "avx512bw", "avx512vl", }, .cpuid_eax =3D 7, @@ -3467,6 +3492,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x14: { + /* Intel Processor Trace Enumeration */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || + !kvm_enabled()) { + break; + } + + if (count =3D=3D 0) { + *eax =3D INTEL_PT_MAX_SUBLEAF; + *ebx =3D INTEL_PT_MINIMAL_EBX; + *ecx =3D INTEL_PT_MINIMAL_ECX; + } else if (count =3D=3D 1) { + *eax =3D INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; + *ebx =3D INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff @@ -4097,6 +4143,34 @@ static int x86_cpu_filter_features(X86CPU *cpu) } } =20 + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && + kvm_enabled()) { + KVMState *s =3D CPU(cpu)->kvm_state; + uint32_t eax_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); + uint32_t ebx_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); + uint32_t ecx_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); + uint32_t eax_1 =3D kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); + uint32_t ebx_1 =3D kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); + + if (!eax_0 || + ((ebx_0 & INTEL_PT_MINIMAL_EBX) !=3D INTEL_PT_MINIMAL_EBX) || + ((ecx_0 & INTEL_PT_MINIMAL_ECX) !=3D INTEL_PT_MINIMAL_ECX) || + ((eax_1 & INTEL_PT_MTC_BITMAP) !=3D INTEL_PT_MTC_BITMAP) || + ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < + INTEL_PT_ADDR_RANGES_NUM) || + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=3D + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) { + /* + * Processor Trace capabilities aren't configurable, so if the + * host can't emulate the capabilities we report on + * cpu_x86_cpuid(), intel-pt can't be enabled on the current h= ost. + */ + env->features[FEAT_7_0_EBX] &=3D ~CPUID_7_0_EBX_INTEL_PT; + cpu->filtered_features[FEAT_7_0_EBX] |=3D CPUID_7_0_EBX_INTEL_= PT; + rv =3D 1; + } + } + return rv; } =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 44ee524188..f5d3d73ed6 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -869,6 +869,29 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; + case 0x14: { + uint32_t times; + + c->function =3D i; + c->index =3D 0; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + times =3D c->eax; + + for (j =3D 1; j <=3D times; ++j) { + if (cpuid_i =3D=3D KVM_MAX_CPUID_ENTRIES) { + fprintf(stderr, "cpuid_data is full, no space for " + "cpuid(eax:0x14,ecx:0x%x)\n", j); + abort(); + } + c =3D &cpuid_data.entries[cpuid_i++]; + c->function =3D i; + c->index =3D j; + c->flags =3D KVM_CPUID_FLAG_SIGNIFCANT_INDEX; + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->ed= x); + } + break; + } default: c->function =3D i; c->flags =3D 0; --=20 2.14.3 From nobody Sun May 5 21:36:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Chao Peng Add Intel Processor Trace related definition. It also add corresponding part to kvm_get/set_msr and vmstate. Signed-off-by: Chao Peng Signed-off-by: Luwei Kang Message-Id: <1520182116-16485-2-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 22 ++++++++++++++++++++++ target/i386/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/i386/machine.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ec2a771299..0c3f51445e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -415,6 +415,21 @@ typedef enum X86Seg { #define MSR_MC0_ADDR 0x402 #define MSR_MC0_MISC 0x403 =20 +#define MSR_IA32_RTIT_OUTPUT_BASE 0x560 +#define MSR_IA32_RTIT_OUTPUT_MASK 0x561 +#define MSR_IA32_RTIT_CTL 0x570 +#define MSR_IA32_RTIT_STATUS 0x571 +#define MSR_IA32_RTIT_CR3_MATCH 0x572 +#define MSR_IA32_RTIT_ADDR0_A 0x580 +#define MSR_IA32_RTIT_ADDR0_B 0x581 +#define MSR_IA32_RTIT_ADDR1_A 0x582 +#define MSR_IA32_RTIT_ADDR1_B 0x583 +#define MSR_IA32_RTIT_ADDR2_A 0x584 +#define MSR_IA32_RTIT_ADDR2_B 0x585 +#define MSR_IA32_RTIT_ADDR3_A 0x586 +#define MSR_IA32_RTIT_ADDR3_B 0x587 +#define MAX_RTIT_ADDRS 8 + #define MSR_EFER 0xc0000080 =20 #define MSR_EFER_SCE (1 << 0) @@ -1157,6 +1172,13 @@ typedef struct CPUX86State { uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; =20 + uint64_t msr_rtit_ctrl; + uint64_t msr_rtit_status; + uint64_t msr_rtit_output_base; + uint64_t msr_rtit_output_mask; + uint64_t msr_rtit_cr3_match; + uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f5d3d73ed6..d996cca68b 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1815,6 +1815,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); } } + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + int addr_num =3D kvm_arch_get_supported_cpuid(kvm_state, + 0x14, 1, R_EAX) & 0x7; + + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, + env->msr_rtit_ctrl); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, + env->msr_rtit_status); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, + env->msr_rtit_output_base); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, + env->msr_rtit_output_mask); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, + env->msr_rtit_cr3_match); + for (i =3D 0; i < addr_num; i++) { + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, + env->msr_rtit_addrs[i]); + } + } =20 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ @@ -2128,6 +2147,20 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { + int addr_num =3D + kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; + + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); + for (i =3D 0; i < addr_num; i++) { + kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); + } + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -2368,6 +2401,24 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_SPEC_CTRL: env->spec_ctrl =3D msrs[i].data; break; + case MSR_IA32_RTIT_CTL: + env->msr_rtit_ctrl =3D msrs[i].data; + break; + case MSR_IA32_RTIT_STATUS: + env->msr_rtit_status =3D msrs[i].data; + break; + case MSR_IA32_RTIT_OUTPUT_BASE: + env->msr_rtit_output_base =3D msrs[i].data; + break; + case MSR_IA32_RTIT_OUTPUT_MASK: + env->msr_rtit_output_mask =3D msrs[i].data; + break; + case MSR_IA32_RTIT_CR3_MATCH: + env->msr_rtit_cr3_match =3D msrs[i].data; + break; + case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: + env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] =3D msrs[i]= .data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 361c05aedf..c05fe6fb1a 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -837,6 +837,43 @@ static const VMStateDescription vmstate_spec_ctrl =3D { } }; =20 +static bool intel_pt_enable_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + int i; + + if (env->msr_rtit_ctrl || env->msr_rtit_status || + env->msr_rtit_output_base || env->msr_rtit_output_mask || + env->msr_rtit_cr3_match) { + return true; + } + + for (i =3D 0; i < MAX_RTIT_ADDRS; i++) { + if (env->msr_rtit_addrs[i]) { + return true; + } + } + + return false; +} + +static const VMStateDescription vmstate_msr_intel_pt =3D { + .name =3D "cpu/intel_pt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D intel_pt_enable_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU), + VMSTATE_UINT64(env.msr_rtit_status, X86CPU), + VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU), + VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU), + VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU), + VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -957,6 +994,7 @@ VMStateDescription vmstate_x86_cpu =3D { #endif &vmstate_spec_ctrl, &vmstate_mcg_ext_ctl, + &vmstate_msr_intel_pt, NULL } }; --=20 2.14.3