From nobody Tue Apr 15 19:53:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520619434147361.6383043077775; Fri, 9 Mar 2018 10:17:14 -0800 (PST) Received: from localhost ([::1]:47191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euMZt-0001Lr-A4 for importer@patchew.org; Fri, 09 Mar 2018 13:17:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euLmv-0008SO-NL for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1euLmt-00067C-Nj for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:37 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1euLmt-00060G-EH for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:35 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1euLmk-00074Y-E1 for qemu-devel@nongnu.org; Fri, 09 Mar 2018 17:26:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:26:02 +0000 Message-Id: <20180309172622.4277-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309172622.4277-1-peter.maydell@linaro.org> References: <20180309172622.4277-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/25] Implement support for i.MX7 Sabre board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Andrey Smirnov Implement code needed to set up emulation of MCIMX7SABRE board from NXP. For more info about the HW see: https://www.nxp.com/support/developer-resources/hardware-development-tools/= sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-7d= ual-applications-processors:MCIMX7SABRE Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daud=C3=A9 Cc: Marcel Apfelbaum Cc: Michael S. Tsirkin Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Andrey Smirnov Signed-off-by: Peter Maydell --- hw/arm/Makefile.objs | 2 +- hw/arm/mcimx7d-sabre.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 hw/arm/mcimx7d-sabre.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index fcf764f373..48474c3394 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -22,4 +22,4 @@ obj-$(CONFIG_MPS2) +=3D mps2.o obj-$(CONFIG_MPS2) +=3D mps2-tz.o obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o obj-$(CONFIG_IOTKIT) +=3D iotkit.o -obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o +obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c new file mode 100644 index 0000000000..95fb409d9c --- /dev/null +++ b/hw/arm/mcimx7d-sabre.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018, Impinj, Inc. + * + * MCIMX7D_SABRE Board System emulation. + * + * Author: Andrey Smirnov + * + * This code is licensed under the GPL, version 2 or later. + * See the file `COPYING' in the top level directory. + * + * It (partially) emulates a mcimx7d_sabre board, with a Freescale + * i.MX7 SoC + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/fsl-imx7.h" +#include "hw/boards.h" +#include "sysemu/sysemu.h" +#include "sysemu/device_tree.h" +#include "qemu/error-report.h" +#include "sysemu/qtest.h" +#include "net/net.h" + +typedef struct { + FslIMX7State soc; + MemoryRegion ram; +} MCIMX7Sabre; + +static void mcimx7d_sabre_init(MachineState *machine) +{ + static struct arm_boot_info boot_info; + MCIMX7Sabre *s =3D g_new0(MCIMX7Sabre, 1); + Object *soc; + int i; + + if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)= ", + machine->ram_size, FSL_IMX7_MMDC_SIZE); + exit(1); + } + + boot_info =3D (struct arm_boot_info) { + .loader_start =3D FSL_IMX7_MMDC_ADDR, + .board_id =3D -1, + .ram_size =3D machine->ram_size, + .kernel_filename =3D machine->kernel_filename, + .kernel_cmdline =3D machine->kernel_cmdline, + .initrd_filename =3D machine->initrd_filename, + .nb_cpus =3D smp_cpus, + }; + + object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7); + soc =3D OBJECT(&s->soc); + object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal); + object_property_set_bool(soc, true, "realized", &error_fatal); + + memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram= ", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), + FSL_IMX7_MMDC_ADDR, &s->ram); + + for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { + BusState *bus; + DeviceState *carddev; + DriveInfo *di; + BlockBackend *blk; + + di =3D drive_get_next(IF_SD); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + bus =3D qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); + carddev =3D qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, + "realized", &error_fatal); + } + + if (!qtest_enabled()) { + arm_load_kernel(&s->soc.cpu[0], &boot_info); + } +} + +static void mcimx7d_sabre_machine_init(MachineClass *mc) +{ + mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex A7)"; + mc->init =3D mcimx7d_sabre_init; + mc->max_cpus =3D FSL_IMX7_NUM_CPUS; +} +DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init) --=20 2.16.2