From nobody Tue Apr 15 19:51:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520617691920117.56469084052549; Fri, 9 Mar 2018 09:48:11 -0800 (PST) Received: from localhost ([::1]:46972 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euM7n-0001YR-3y for importer@patchew.org; Fri, 09 Mar 2018 12:48:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59712) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euLmx-0008Tm-By for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1euLmv-00068j-7E for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:39 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:47000) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1euLmu-00064P-VR for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:37 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1euLmh-00073e-Oc for qemu-devel@nongnu.org; Fri, 09 Mar 2018 17:26:23 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:25:58 +0000 Message-Id: <20180309172622.4277-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309172622.4277-1-peter.maydell@linaro.org> References: <20180309172622.4277-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/25] target/arm: Add a core count property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The cortex A53 TRM specifies that bits 24 and 25 of the L2CTLR register specify the number of cores in the processor, not the total number of cores in the system. To report this correctly on machines with multiple CPU clusters (ARM's big.LITTLE or Xilinx's ZynqMP) we need to allow the machine to overwrite this value. To do this let's add an optional property. Signed-off-by: Alistair Francis Message-id: ef01d95c0759e88f47f22d11b14c91512a658b4f.1520018138.git.alistai= r.francis@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/cpu.c | 6 ++++++ target/arm/cpu64.c | 6 ++++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8dd6b788df..3fa8fdad21 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -745,6 +745,11 @@ struct ARMCPU { /* Uniprocessor system with MP extensions */ bool mp_is_up; =20 + /* Specify the number of cores in this CPU cluster. Used for the L2CTLR + * register. + */ + int32_t core_count; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b77aaa445..3e4e9f1873 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -939,6 +939,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) cs->num_ases =3D 1; } cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); + + /* No core_count specified, default to smp_cpus. */ + if (cpu->core_count =3D=3D -1) { + cpu->core_count =3D smp_cpus; + } #endif =20 qemu_init_vcpu(cs); @@ -1765,6 +1770,7 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), + DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4228713b19..dd9ba973f7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -42,8 +42,10 @@ static inline void unset_feature(CPUARMState *env, int f= eature) #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { - /* Number of processors is in [25:24]; otherwise we RAZ */ - return (smp_cpus - 1) << 24; + ARMCPU *cpu =3D arm_env_get_cpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; } #endif =20 --=20 2.16.2