From nobody Tue Apr 15 19:52:15 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1520617349156818.5865670702385; Fri, 9 Mar 2018 09:42:29 -0800 (PST) Received: from localhost ([::1]:46903 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euM2C-0004xw-Ne for importer@patchew.org; Fri, 09 Mar 2018 12:42:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59562) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euLms-0008Or-Kw for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1euLmq-00064L-Rg for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:34 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1euLmq-00060G-Gu for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:32 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1euLmn-00075g-N4 for qemu-devel@nongnu.org; Fri, 09 Mar 2018 17:26:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:26:07 +0000 Message-Id: <20180309172622.4277-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309172622.4277-1-peter.maydell@linaro.org> References: <20180309172622.4277-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/25] aarch64-linux-user: Add support for SVE signal frame records X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Depending on the currently selected size of the SVE vector registers, we can either store the data within the "standard" allocation, or we may beedn to allocate additional space with an EXTRA record. Signed-off-by: Richard Henderson Message-id: 20180303143823.27055-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/signal.c | 210 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 192 insertions(+), 18 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index f8bc0aa397..2ce5d7a3c7 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1455,6 +1455,34 @@ struct target_extra_context { uint32_t reserved[3]; }; =20 +#define TARGET_SVE_MAGIC 0x53564501 + +struct target_sve_context { + struct target_aarch64_ctx head; + uint16_t vl; + uint16_t reserved[3]; + /* The actual SVE data immediately follows. It is layed out + * according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of + * the original struct pointer. + */ +}; + +#define TARGET_SVE_VQ_BYTES 16 + +#define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8)) + +#define TARGET_SVE_SIG_REGS_OFFSET \ + QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES) +#define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N)) +#define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \ + (TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (= N)) +#define TARGET_SVE_SIG_FFR_OFFSET(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 16)) +#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \ + (TARGET_SVE_SIG_PREG_OFFSET(VQ, 17)) + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -1529,6 +1557,34 @@ static void target_setup_end_record(struct target_aa= rch64_ctx *end) __put_user(0, &end->size); } =20 +static void target_setup_sve_record(struct target_sve_context *sve, + CPUARMState *env, int vq, int size) +{ + int i, j; + + __put_user(TARGET_SVE_MAGIC, &sve->head.magic); + __put_user(size, &sve->head.size); + __put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl); + + /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + * at a subsequent address. This corresponds to a little-endian store + * of our 64-bit hunks. + */ + for (i =3D 0; i < 32; ++i) { + uint64_t *z =3D (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __put_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i =3D 0; i <=3D 16; ++i) { + uint16_t *p =3D (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j =3D 0; j < vq; ++j) { + uint64_t r =3D env->vfp.pregs[i].p[j >> 2]; + __put_user_e(r >> ((j & 3) * 16), p + j, le); + } + } +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -1572,14 +1628,45 @@ static void target_restore_fpsimd_record(CPUARMStat= e *env, } } =20 +static void target_restore_sve_record(CPUARMState *env, + struct target_sve_context *sve, int = vq) +{ + int i, j; + + /* Note that SVE regs are stored as a byte stream, with each byte elem= ent + * at a subsequent address. This corresponds to a little-endian load + * of our 64-bit hunks. + */ + for (i =3D 0; i < 32; ++i) { + uint64_t *z =3D (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i); + for (j =3D 0; j < vq * 2; ++j) { + __get_user_e(env->vfp.zregs[i].d[j], z + j, le); + } + } + for (i =3D 0; i <=3D 16; ++i) { + uint16_t *p =3D (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i); + for (j =3D 0; j < vq; ++j) { + uint16_t r; + __get_user_e(r, p + j, le); + if (j & 3) { + env->vfp.pregs[i].p[j >> 2] |=3D (uint64_t)r << ((j & 3) *= 16); + } else { + env->vfp.pregs[i].p[j >> 2] =3D r; + } + } + } +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { struct target_aarch64_ctx *ctx, *extra =3D NULL; struct target_fpsimd_context *fpsimd =3D NULL; + struct target_sve_context *sve =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; bool err =3D false; + int vq =3D 0, sve_size =3D 0; =20 target_restore_general_frame(env, sf); =20 @@ -1611,6 +1698,18 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd =3D (struct target_fpsimd_context *)ctx; break; =20 + case TARGET_SVE_MAGIC: + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); + if (!sve && size =3D=3D sve_size) { + sve =3D (struct target_sve_context *)ctx; + break; + } + } + err =3D true; + goto exit; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { err =3D true; @@ -1640,12 +1739,18 @@ static int target_restore_sigframe(CPUARMState *env, err =3D true; } =20 + /* SVE data, if present, overwrites FPSIMD data. */ + if (sve) { + target_restore_sve_record(env, sve, vq); + } + exit: unlock_user(extra, extra_datap, 0); return err; } =20 -static abi_ulong get_sigframe(struct target_sigaction *ka, CPUARMState *en= v) +static abi_ulong get_sigframe(struct target_sigaction *ka, + CPUARMState *env, int size) { abi_ulong sp; =20 @@ -1658,30 +1763,97 @@ static abi_ulong get_sigframe(struct target_sigacti= on *ka, CPUARMState *env) sp =3D target_sigaltstack_used.ss_sp + target_sigaltstack_used.ss_= size; } =20 - sp =3D (sp - sizeof(struct target_rt_sigframe)) & ~15; + sp =3D (sp - size) & ~15; =20 return sp; } =20 +typedef struct { + int total_size; + int extra_base; + int extra_size; + int std_end_ofs; + int extra_ofs; + int extra_end_ofs; +} target_sigframe_layout; + +static int alloc_sigframe_space(int this_size, target_sigframe_layout *l) +{ + /* Make sure there will always be space for the end marker. */ + const int std_size =3D sizeof(struct target_rt_sigframe) + - sizeof(struct target_aarch64_ctx); + int this_loc =3D l->total_size; + + if (l->extra_base) { + /* Once we have begun an extra space, all allocations go there. */ + l->extra_size +=3D this_size; + } else if (this_size + this_loc > std_size) { + /* This allocation does not fit in the standard space. */ + /* Allocate the extra record. */ + l->extra_ofs =3D this_loc; + l->total_size +=3D sizeof(struct target_extra_context); + + /* Allocate the standard end record. */ + l->std_end_ofs =3D l->total_size; + l->total_size +=3D sizeof(struct target_aarch64_ctx); + + /* Allocate the requested record. */ + l->extra_base =3D this_loc =3D l->total_size; + l->extra_size =3D this_size; + } + l->total_size +=3D this_size; + + return this_loc; +} + static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *se= t, CPUARMState *env) { - int size =3D offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__res= erved); - int fpsimd_ofs, end1_ofs, fr_ofs, end2_ofs =3D 0; - int extra_ofs =3D 0, extra_base =3D 0, extra_size =3D 0; + target_sigframe_layout layout =3D { + /* Begin with the size pointing to the reserved space. */ + .total_size =3D offsetof(struct target_rt_sigframe, + uc.tuc_mcontext.__reserved), + }; + int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, vq =3D 0, sve_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; abi_ulong frame_addr, return_addr; =20 - fpsimd_ofs =3D size; - size +=3D sizeof(struct target_fpsimd_context); - end1_ofs =3D size; - size +=3D sizeof(struct target_aarch64_ctx); - fr_ofs =3D size; - size +=3D sizeof(struct target_rt_frame_record); + /* FPSIMD record is always in the standard space. */ + fpsimd_ofs =3D alloc_sigframe_space(sizeof(struct target_fpsimd_contex= t), + &layout); =20 - frame_addr =3D get_sigframe(ka, env); + /* SVE state needs saving only if it exists. */ + if (arm_feature(env, ARM_FEATURE_SVE)) { + vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); + sve_ofs =3D alloc_sigframe_space(sve_size, &layout); + } + + if (layout.extra_ofs) { + /* Reserve space for the extra end marker. The standard end marker + * will have been allocated when we allocated the extra record. + */ + layout.extra_end_ofs + =3D alloc_sigframe_space(sizeof(struct target_aarch64_ctx), &l= ayout); + } else { + /* Reserve space for the standard end marker. + * Do not use alloc_sigframe_space because we cheat + * std_size therein to reserve space for this. + */ + layout.std_end_ofs =3D layout.total_size; + layout.total_size +=3D sizeof(struct target_aarch64_ctx); + } + + /* Reserve space for the return code. On a real system this would + * be within the VDSO. So, despite the name this is not a "real" + * record within the frame. + */ + fr_ofs =3D layout.total_size; + layout.total_size +=3D sizeof(struct target_rt_frame_record); + + frame_addr =3D get_sigframe(ka, env, layout.total_size); trace_user_setup_frame(env, frame_addr); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv; @@ -1689,13 +1861,15 @@ static void target_setup_frame(int usig, struct tar= get_sigaction *ka, =20 target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); - if (extra_ofs) { - target_setup_extra_record((void *)frame + extra_ofs, - frame_addr + extra_base, extra_size); + target_setup_end_record((void *)frame + layout.std_end_ofs); + if (layout.extra_ofs) { + target_setup_extra_record((void *)frame + layout.extra_ofs, + frame_addr + layout.extra_base, + layout.extra_size); + target_setup_end_record((void *)frame + layout.extra_end_ofs); } - target_setup_end_record((void *)frame + end1_ofs); - if (end2_ofs) { - target_setup_end_record((void *)frame + end2_ofs); + if (sve_ofs) { + target_setup_sve_record((void *)frame + sve_ofs, env, vq, sve_size= ); } =20 /* Set up the stack frame for unwinding. */ --=20 2.16.2