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Tsirkin" , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Marcel Apfelbaum , Aurelien Jarno , Mark Cave-Ayland , Alexey Kardashevskiy , Thomas Huth Date: Mon, 5 Mar 2018 18:19:11 -0300 Message-Id: <20180305211928.466-6-f4bug@amsat.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180305211928.466-1-f4bug@amsat.org> References: <20180305211928.466-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RFC PATCH v2 05/22] hw/isa/pc87312: Use uint16_t for the ISA I/O base address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, "open list:PReP" , Guan Xuetao , Yongbok Kim , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This matches the isa_register_ioport() prototype. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/isa/pc87312.h | 2 +- hw/isa/pc87312.c | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/include/hw/isa/pc87312.h b/include/hw/isa/pc87312.h index 710eb1c807..b65b219a8a 100644 --- a/include/hw/isa/pc87312.h +++ b/include/hw/isa/pc87312.h @@ -34,7 +34,7 @@ typedef struct PC87312State { ISADevice dev; =20 - uint32_t iobase; + uint16_t iobase; uint8_t config; /* initial configuration */ =20 struct { diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c index e9edbc6c50..105c23e680 100644 --- a/hw/isa/pc87312.c +++ b/hw/isa/pc87312.c @@ -69,9 +69,9 @@ static inline bool is_parallel_enabled(PC87312State *s) return s->regs[REG_FER] & FER_PARALLEL_EN; } =20 -static const uint32_t parallel_base[] =3D { 0x378, 0x3bc, 0x278, 0x00 }; +static const uint16_t parallel_base[] =3D { 0x378, 0x3bc, 0x278, 0x00 }; =20 -static inline uint32_t get_parallel_iobase(PC87312State *s) +static inline uint16_t get_parallel_iobase(PC87312State *s) { return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR]; } @@ -92,12 +92,12 @@ static inline uint32_t get_parallel_irq(PC87312State *s) =20 /* UARTs */ =20 -static const uint32_t uart_base[2][4] =3D { +static const uint16_t uart_base[2][4] =3D { { 0x3e8, 0x338, 0x2e8, 0x220 }, { 0x2e8, 0x238, 0x2e0, 0x228 } }; =20 -static inline uint32_t get_uart_iobase(PC87312State *s, int i) +static inline uint16_t get_uart_iobase(PC87312State *s, int i) { int idx; idx =3D (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; @@ -130,7 +130,7 @@ static inline bool is_fdc_enabled(PC87312State *s) return s->regs[REG_FER] & FER_FDC_EN; } =20 -static inline uint32_t get_fdc_iobase(PC87312State *s) +static inline uint16_t get_fdc_iobase(PC87312State *s) { return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0; } @@ -143,7 +143,7 @@ static inline bool is_ide_enabled(PC87312State *s) return s->regs[REG_FER] & FER_IDE_EN; } =20 -static inline uint32_t get_ide_iobase(PC87312State *s) +static inline uint16_t get_ide_iobase(PC87312State *s) { return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0; } @@ -373,7 +373,7 @@ static const VMStateDescription vmstate_pc87312 =3D { }; =20 static Property pc87312_properties[] =3D { - DEFINE_PROP_UINT32("iobase", PC87312State, iobase, 0x398), + DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398), DEFINE_PROP_UINT8("config", PC87312State, config, 1), DEFINE_PROP_END_OF_LIST() }; --=20 2.16.2