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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 10/30] hw/ppc: use the BYTE-based definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:PReP" , qemu-devel@nongnu.org, Alexander Graf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 It eases code review, unit is explicit. Patch generated using: $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/ and modified manually. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: David Gibson --- include/hw/ppc/spapr.h | 2 +- hw/pci-host/prep.c | 2 +- hw/ppc/e500.c | 8 ++++---- hw/ppc/mac_oldworld.c | 7 +++---- hw/ppc/ppc405_boards.c | 8 ++++---- hw/ppc/ppc405_uc.c | 6 +++--- hw/ppc/ppc4xx_devs.c | 21 +++++++++++---------- hw/ppc/ppce500_spin.c | 2 +- hw/ppc/prep.c | 2 +- hw/ppc/rs6000_mc.c | 12 ++++++------ hw/ppc/virtex_ml507.c | 4 ++-- 11 files changed, 37 insertions(+), 37 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 36942b378d..896eb1b0b0 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -746,7 +746,7 @@ int spapr_rng_populate_dt(void *fdt); #define SPAPR_MAX_RAM_SLOTS 32 =20 /* 1GB alignment for hotplug memory region */ -#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30) +#define SPAPR_HOTPLUG_MEM_ALIGN (1 * G_BYTE) =20 /* * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 01f67f9db1..d06498e131 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -70,7 +70,7 @@ typedef struct PRePPCIState { int contiguous_map; } PREPPCIState; =20 -#define BIOS_SIZE (1024 * 1024) +#define BIOS_SIZE (1 * M_BYTE) =20 static inline uint32_t raven_pci_io_config(hwaddr addr) { diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index a40d3ec3e3..02675c7be4 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -45,7 +45,7 @@ #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" #define DTC_LOAD_PAD 0x1800000 #define DTC_PAD_MASK 0xFFFFF -#define DTB_MAX_SIZE (8 * 1024 * 1024) +#define DTB_MAX_SIZE (8 * M_BYTE) #define INITRD_LOAD_PAD 0x2000000 #define INITRD_PAD_MASK 0xFFFFFF =20 @@ -597,7 +597,7 @@ static int ppce500_prep_device_tree(MachineState *machi= ne, /* Create -kernel TLB entries for BookE. */ hwaddr booke206_page_size_to_tlb(uint64_t size) { - return 63 - clz64(size >> 10); + return 63 - clz64(size / K_BYTE); } =20 static int booke206_initial_map_tsize(CPUPPCState *env) @@ -913,9 +913,9 @@ void ppce500_init(MachineState *machine, PPCE500Params = *params) /* Register spinning region */ sysbus_create_simple("e500-spin", params->spin_base, NULL); =20 - if (cur_base < (32 * 1024 * 1024)) { + if (cur_base < 32 * M_BYTE) { /* u-boot occupies memory up to 32MB, so load blobs above */ - cur_base =3D (32 * 1024 * 1024); + cur_base =3D 32 * M_BYTE; } =20 if (params->has_mpc8xxx_gpio) { diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index c245251c5c..76bdc2c11d 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -118,10 +118,9 @@ static void ppc_heathrow_init(MachineState *machine) } =20 /* allocate RAM */ - if (ram_size > (2047 << 20)) { - fprintf(stderr, - "qemu: Too much memory for this machine: %d MB, maximum 20= 47 MB\n", - ((unsigned int)ram_size / (1 << 20))); + if (ram_size > 2047 * M_BYTE) { + error_report("Too much memory for this machine: %llu MB, " + "maximum 2047 MB", ram_size / M_BYTE); exit(1); } =20 diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 0b658931ee..8c742449b8 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -41,7 +41,7 @@ #include "exec/address-spaces.h" =20 #define BIOS_FILENAME "ppc405_rom.bin" -#define BIOS_SIZE (2048 * 1024) +#define BIOS_SIZE (2 * M_BYTE) =20 #define KERNEL_LOAD_ADDR 0x00000000 #define INITRD_LOAD_ADDR 0x01800000 @@ -217,14 +217,14 @@ static void ref405ep_init(MachineState *machine) memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); ram_bases[1] =3D 0x00000000; ram_sizes[1] =3D 0x00000000; - ram_size =3D 128 * 1024 * 1024; + ram_size =3D 128 * M_BYTE; #ifdef DEBUG_BOARD_INIT printf("%s: register cpu\n", __func__); #endif env =3D ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename =3D=3D NULL ? 0 : = 1); /* allocate SRAM */ - sram_size =3D 512 * 1024; + sram_size =3D 512 * K_BYTE; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, &error_fatal); memory_region_add_subregion(sysmem, 0xFFF00000, sram); @@ -590,7 +590,7 @@ static void taihu_405ep_init(MachineState *machine) =20 bios_size =3D blk_getlength(blk); /* XXX: should check that size is 32MB */ - bios_size =3D 32 * 1024 * 1024; + bios_size =3D 32 * M_BYTE; fl_sectors =3D (bios_size + 65535) >> 16; #ifdef DEBUG_BOARD_INIT printf("Register parallel flash %d size %lx" diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 205ebcea93..0e9d5b0ff9 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -983,10 +983,10 @@ static void ppc405_ocm_init(CPUPPCState *env) =20 ocm =3D g_malloc0(sizeof(ppc405_ocm_t)); /* XXX: Size is 4096 or 0x04000000 */ - memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096, + memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * K_BYTE, &error_fatal); - memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->= isarc_ram, - 0, 4096); + memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", + &ocm->isarc_ram, 0, 4 * K_BYTE); qemu_register_reset(&ocm_reset, ocm); ppc_dcr_register(env, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 2e963894fe..52de988b13 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -29,6 +29,7 @@ #include "hw/boards.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "qemu/error-report.h" =20 #define DEBUG_UIC =20 @@ -353,25 +354,25 @@ static uint32_t sdram_bcr (hwaddr ram_base, uint32_t bcr; =20 switch (ram_size) { - case (4 * 1024 * 1024): + case 4 * M_BYTE: bcr =3D 0x00000000; break; - case (8 * 1024 * 1024): + case 8 * M_BYTE: bcr =3D 0x00020000; break; - case (16 * 1024 * 1024): + case 16 * M_BYTE: bcr =3D 0x00040000; break; - case (32 * 1024 * 1024): + case 32 * M_BYTE: bcr =3D 0x00060000; break; - case (64 * 1024 * 1024): + case 64 * M_BYTE: bcr =3D 0x00080000; break; - case (128 * 1024 * 1024): + case 128 * M_BYTE: bcr =3D 0x000A0000; break; - case (256 * 1024 * 1024): + case 256 * M_BYTE: bcr =3D 0x000C0000; break; default: @@ -399,7 +400,7 @@ static target_ulong sdram_size (uint32_t bcr) if (sh =3D=3D 7) size =3D -1; else - size =3D (4 * 1024 * 1024) << sh; + size =3D (4 * M_BYTE) << sh; =20 return size; } @@ -702,8 +703,8 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int= nr_banks, =20 ram_size -=3D size_left; if (size_left) { - printf("Truncating memory to %d MiB to fit SDRAM controller limits= .\n", - (int)(ram_size >> 20)); + error_report("Truncating memory to %llu MiB to fit SDRAM " + "controller limits", ram_size / M_BYTE); } =20 memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_si= ze); diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 69ca2d0e42..b6d224c45b 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -89,7 +89,7 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data) PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; SpinInfo *curspin =3D data.host_ptr; - hwaddr map_size =3D 64 * 1024 * 1024; + hwaddr map_size =3D 64 * M_BYTE; hwaddr map_start; =20 cpu_synchronize_state(cs); diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index f7c0a48558..eae475a34d 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -59,7 +59,7 @@ =20 #define CFG_ADDR 0xf0000510 =20 -#define BIOS_SIZE (1024 * 1024) +#define BIOS_SIZE (1 * M_BYTE) #define BIOS_FILENAME "ppc_rom.bin" #define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c index b6135650bd..6999994fe4 100644 --- a/hw/ppc/rs6000_mc.c +++ b/hw/ppc/rs6000_mc.c @@ -109,7 +109,7 @@ static void rs6000mc_port0820_write(void *opaque, uint3= 2_t addr, uint32_t val) size =3D end_address - start_address; memory_region_set_enabled(&s->simm[socket - 1], size !=3D 0); memory_region_set_address(&s->simm[socket - 1], - start_address * 8 * 1024 * 1024); + start_address * 8 * M_BYTE); } } } @@ -140,7 +140,7 @@ static void rs6000mc_realize(DeviceState *dev, Error **= errp) { RS6000MCState *s =3D RS6000MC_DEVICE(dev); int socket =3D 0; - unsigned int ram_size =3D s->ram_size / (1024 * 1024); + unsigned int ram_size =3D s->ram_size / M_BYTE; =20 while (socket < 6) { if (ram_size >=3D 64) { @@ -163,8 +163,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **= errp) char name[] =3D "simm.?"; name[5] =3D socket + '0'; memory_region_allocate_system_memory(&s->simm[socket], OBJECT(= dev), - name, s->simm_size[socket] - * 1024 * 1024); + name, + s->simm_size[socket] * M_= BYTE); memory_region_add_subregion_overlap(get_system_memory(), 0, &s->simm[socket], socket); } @@ -172,8 +172,8 @@ static void rs6000mc_realize(DeviceState *dev, Error **= errp) if (ram_size) { /* unable to push all requested RAM in SIMMs */ error_setg(errp, "RAM size incompatible with this board. " - "Try again with something else, like %d MB", - s->ram_size / 1024 / 1024 - ram_size); + "Try again with something else, like %lld MB", + s->ram_size / M_BYTE - ram_size); return; } =20 diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 77a1778e07..dcfb6c2670 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -47,7 +47,7 @@ #include "sysemu/block-backend.h" =20 #define EPAPR_MAGIC (0x45504150) -#define FLASH_SIZE (16 * 1024 * 1024) +#define FLASH_SIZE (16 * M_BYTE) =20 #define INTC_BASEADDR 0x81800000 #define UART16550_BASEADDR 0x83e01003 @@ -237,7 +237,7 @@ static void virtex_init(MachineState *machine) dinfo =3D drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZ= E, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - (64 * 1024), FLASH_SIZE >> 16, + 64 * K_BYTE, FLASH_SIZE >> 16, 1, 0x89, 0x18, 0x0000, 0x0, 1); =20 cpu_irq =3D (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; --=20 2.16.2