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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 2 Mar 2018 11:06:39 +0000
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Subject: [Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and
2reg_scalar extension
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From: Richard Henderson <richard.henderson@linaro.org>
Happily, the bits are in the same places compared to a32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180228193125.20577-16-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3ad8b4031c..ba6ab7d287 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10774,7 +10774,19 @@ static void disas_thumb2_insn(DisasContext *s, uin=
t32_t insn)
default_exception_el(s));
break;
}
- if (((insn >> 24) & 3) =3D=3D 3) {
+ if ((insn & 0xfe000a00) =3D=3D 0xfc000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_3same_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if ((insn & 0xff000a00) =3D=3D 0xfe000800
+ && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ /* The Thumb2 and ARM encodings are identical. */
+ if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
+ goto illegal_op;
+ }
+ } else if (((insn >> 24) & 3) =3D=3D 3) {
/* Translate into the equivalent ARM encoding. */
insn =3D (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 =
<< 28);
if (disas_neon_data_insn(s, insn)) {
--=20
2.16.2