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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 2 Mar 2018 11:06:35 +0000
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Subject: [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd
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From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180228193125.20577-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 7 ++++
target/arm/translate-a64.c | 48 ++++++++++++++++++++++-
target/arm/vec_helper.c | 97 ++++++++++++++++++++++++++++++++++++++++++=
++++
3 files changed, 151 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 7f0d3b2d84..1e2d7025de 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -578,6 +578,13 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
=20
+DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcadds, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fcaddd, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e4d2d548ba..efed4fd9d2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -713,6 +713,21 @@ static void gen_gvec_op3_env(DisasContext *s, bool is_=
q, int rd,
is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
}
=20
+/* Expand a 3-operand + fpstatus pointer + simd data value operation using
+ * an out-of-line helper.
+ */
+static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
+ int rm, bool is_fp16, int data,
+ gen_helper_gvec_3_ptr *fn)
+{
+ TCGv_ptr fpst =3D get_fpstatus_ptr(is_fp16);
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), fpst,
+ is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
+ tcg_temp_free_ptr(fpst);
+}
+
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
* than the 32 bit equivalent.
*/
@@ -10816,7 +10831,7 @@ static void disas_simd_three_reg_same_extra(DisasCo=
ntext *s, uint32_t insn)
int size =3D extract32(insn, 22, 2);
bool u =3D extract32(insn, 29, 1);
bool is_q =3D extract32(insn, 30, 1);
- int feature;
+ int feature, rot;
=20
switch (u * 16 + opcode) {
case 0x10: /* SQRDMLAH (vector) */
@@ -10827,6 +10842,16 @@ static void disas_simd_three_reg_same_extra(DisasC=
ontext *s, uint32_t insn)
}
feature =3D ARM_FEATURE_V8_RDM;
break;
+ case 0xc: /* FCADD, #90 */
+ case 0xe: /* FCADD, #270 */
+ if (size =3D=3D 0
+ || (size =3D=3D 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
+ || (size =3D=3D 3 && !is_q)) {
+ unallocated_encoding(s);
+ return;
+ }
+ feature =3D ARM_FEATURE_V8_FCMA;
+ break;
default:
unallocated_encoding(s);
return;
@@ -10866,6 +10891,27 @@ static void disas_simd_three_reg_same_extra(DisasC=
ontext *s, uint32_t insn)
}
return;
=20
+ case 0xc: /* FCADD, #90 */
+ case 0xe: /* FCADD, #270 */
+ rot =3D extract32(opcode, 1, 1);
+ switch (size) {
+ case 1:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size =3D=3D 1, rot,
+ gen_helper_gvec_fcaddh);
+ break;
+ case 2:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size =3D=3D 1, rot,
+ gen_helper_gvec_fcadds);
+ break;
+ case 3:
+ gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size =3D=3D 1, rot,
+ gen_helper_gvec_fcaddd);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return;
+
default:
g_assert_not_reached();
}
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 3072df4d77..a868ca6aac 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -22,8 +22,21 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
+#include "fpu/softfloat.h"
=20
=20
+/* Note that vector data is stored in host-endian 64-bit chunks,
+ so addressing units smaller than that needs a host-endian fixup. */
+#ifdef HOST_WORDS_BIGENDIAN
+#define H1(x) ((x) ^ 7)
+#define H2(x) ((x) ^ 3)
+#define H4(x) ((x) ^ 1)
+#else
+#define H1(x) (x)
+#define H2(x) (x)
+#define H4(x) (x)
+#endif
+
#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |=3D CPSR_Q
=20
static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz)
@@ -181,3 +194,87 @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void=
*vm,
}
clear_tail(d, opr_sz, simd_maxsz(desc));
}
+
+void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz =3D simd_oprsz(desc);
+ float16 *d =3D vd;
+ float16 *n =3D vn;
+ float16 *m =3D vm;
+ float_status *fpst =3D vfpst;
+ uint32_t neg_real =3D extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag =3D neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<=3D 15;
+ neg_imag <<=3D 15;
+
+ for (i =3D 0; i < opr_sz / 2; i +=3D 2) {
+ float16 e0 =3D n[H2(i)];
+ float16 e1 =3D m[H2(i + 1)] ^ neg_imag;
+ float16 e2 =3D n[H2(i + 1)];
+ float16 e3 =3D m[H2(i)] ^ neg_real;
+
+ d[H2(i)] =3D float16_add(e0, e1, fpst);
+ d[H2(i + 1)] =3D float16_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz =3D simd_oprsz(desc);
+ float32 *d =3D vd;
+ float32 *n =3D vn;
+ float32 *m =3D vm;
+ float_status *fpst =3D vfpst;
+ uint32_t neg_real =3D extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint32_t neg_imag =3D neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<=3D 31;
+ neg_imag <<=3D 31;
+
+ for (i =3D 0; i < opr_sz / 4; i +=3D 2) {
+ float32 e0 =3D n[H4(i)];
+ float32 e1 =3D m[H4(i + 1)] ^ neg_imag;
+ float32 e2 =3D n[H4(i + 1)];
+ float32 e3 =3D m[H4(i)] ^ neg_real;
+
+ d[H4(i)] =3D float32_add(e0, e1, fpst);
+ d[H4(i + 1)] =3D float32_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
+ void *vfpst, uint32_t desc)
+{
+ uintptr_t opr_sz =3D simd_oprsz(desc);
+ float64 *d =3D vd;
+ float64 *n =3D vn;
+ float64 *m =3D vm;
+ float_status *fpst =3D vfpst;
+ uint64_t neg_real =3D extract64(desc, SIMD_DATA_SHIFT, 1);
+ uint64_t neg_imag =3D neg_real ^ 1;
+ uintptr_t i;
+
+ /* Shift boolean to the sign bit so we can xor to negate. */
+ neg_real <<=3D 63;
+ neg_imag <<=3D 63;
+
+ for (i =3D 0; i < opr_sz / 8; i +=3D 2) {
+ float64 e0 =3D n[i];
+ float64 e1 =3D m[i + 1] ^ neg_imag;
+ float64 e2 =3D n[i + 1];
+ float64 e3 =3D m[i] ^ neg_real;
+
+ d[i] =3D float64_add(e0, e1, fpst);
+ d[i + 1] =3D float64_add(e2, e3, fpst);
+ }
+ clear_tail(d, opr_sz, simd_maxsz(desc));
+}
--=20
2.16.2