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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 2 Mar 2018 11:06:31 +0000
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Subject: [Qemu-devel] [PULL 30/39] target/arm: Decode aa32 armv8.1 three same
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From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180228193125.20577-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 86 +++++++++++++++++++++++++++++++++++++++-------=
----
1 file changed, 67 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index aa6dcaa577..05fa6a53f9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -25,6 +25,7 @@
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
#include "arm_ldst.h"
@@ -5374,9 +5375,9 @@ static void gen_neon_narrow_op(int op, int u, int siz=
e,
#define NEON_3R_VPMAX 20
#define NEON_3R_VPMIN 21
#define NEON_3R_VQDMULH_VQRDMULH 22
-#define NEON_3R_VPADD 23
+#define NEON_3R_VPADD_VQRDMLAH 23
#define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
-#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
+#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
@@ -5408,9 +5409,9 @@ static const uint8_t neon_3r_sizes[] =3D {
[NEON_3R_VPMAX] =3D 0x7,
[NEON_3R_VPMIN] =3D 0x7,
[NEON_3R_VQDMULH_VQRDMULH] =3D 0x6,
- [NEON_3R_VPADD] =3D 0x7,
+ [NEON_3R_VPADD_VQRDMLAH] =3D 0x7,
[NEON_3R_SHA] =3D 0xf, /* size field encodes op type */
- [NEON_3R_VFM] =3D 0x5, /* size bit 1 encodes op */
+ [NEON_3R_VFM_VQRDMLSH] =3D 0x7, /* For VFM, size bit 1 encodes op */
[NEON_3R_FLOAT_ARITH] =3D 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_MULTIPLY] =3D 0x5, /* size bit 1 encodes op */
[NEON_3R_FLOAT_CMP] =3D 0x5, /* size bit 1 encodes op */
@@ -5589,6 +5590,22 @@ static const uint8_t neon_2rm_sizes[] =3D {
[NEON_2RM_VCVT_UF] =3D 0x4,
};
=20
+
+/* Expand v8.1 simd helper. */
+static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
+ int q, int rd, int rn, int rm)
+{
+ if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
+ int opr_sz =3D (1 + q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
+ vfp_reg_offset(1, rn),
+ vfp_reg_offset(1, rm), cpu_env,
+ opr_sz, opr_sz, 0, fn);
+ return 0;
+ }
+ return 1;
+}
+
/* Translate a NEON data processing instruction. Return nonzero if the
instruction is invalid.
We process data in a mixture of 32-bit and 64-bit chunks.
@@ -5641,12 +5658,13 @@ static int disas_neon_data_insn(DisasContext *s, ui=
nt32_t insn)
if (q && ((rd | rn | rm) & 1)) {
return 1;
}
- /*
- * The SHA-1/SHA-256 3-register instructions require special treat=
ment
- * here, as their size field is overloaded as an op type selector,=
and
- * they all consume their input in a single pass.
- */
- if (op =3D=3D NEON_3R_SHA) {
+ switch (op) {
+ case NEON_3R_SHA:
+ /* The SHA-1/SHA-256 3-register instructions require special
+ * treatment here, as their size field is overloaded as an
+ * op type selector, and they all consume their input in a
+ * single pass.
+ */
if (!q) {
return 1;
}
@@ -5683,6 +5701,40 @@ static int disas_neon_data_insn(DisasContext *s, uin=
t32_t insn)
tcg_temp_free_ptr(ptr2);
tcg_temp_free_ptr(ptr3);
return 0;
+
+ case NEON_3R_VPADD_VQRDMLAH:
+ if (!u) {
+ break; /* VPADD */
+ }
+ /* VQRDMLAH */
+ switch (size) {
+ case 1:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16,
+ q, rd, rn, rm);
+ case 2:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32,
+ q, rd, rn, rm);
+ }
+ return 1;
+
+ case NEON_3R_VFM_VQRDMLSH:
+ if (!u) {
+ /* VFM, VFMS */
+ if (size =3D=3D 1) {
+ return 1;
+ }
+ break;
+ }
+ /* VQRDMLSH */
+ switch (size) {
+ case 1:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16,
+ q, rd, rn, rm);
+ case 2:
+ return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32,
+ q, rd, rn, rm);
+ }
+ return 1;
}
if (size =3D=3D 3 && op !=3D NEON_3R_LOGIC) {
/* 64-bit element instructions. */
@@ -5768,11 +5820,7 @@ static int disas_neon_data_insn(DisasContext *s, uin=
t32_t insn)
rm =3D rtmp;
}
break;
- case NEON_3R_VPADD:
- if (u) {
- return 1;
- }
- /* Fall through */
+ case NEON_3R_VPADD_VQRDMLAH:
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
pairwise =3D 1;
@@ -5806,8 +5854,8 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
return 1;
}
break;
- case NEON_3R_VFM:
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) {
+ case NEON_3R_VFM_VQRDMLSH:
+ if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
return 1;
}
break;
@@ -6004,7 +6052,7 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
}
}
break;
- case NEON_3R_VPADD:
+ case NEON_3R_VPADD_VQRDMLAH:
switch (size) {
case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
@@ -6103,7 +6151,7 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
}
}
break;
- case NEON_3R_VFM:
+ case NEON_3R_VFM_VQRDMLSH:
{
/* VFMA, VFMS: fused multiply-add */
TCGv_ptr fpstatus =3D get_fpstatus_ptr(1);
--=20
2.16.2