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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 2 Mar 2018 11:06:27 +0000
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Subject: [Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed
size checks
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From: Richard Henderson <richard.henderson@linaro.org>
The integer size check was already outside of the opcode switch;
move the floating-point size check outside as well. Unify the
size vs index adjustment between fp and integer paths.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180228193125.20577-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 65 +++++++++++++++++++++++-------------------=
----
1 file changed, 32 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fc928b61f6..cbb4510e3a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11820,10 +11820,6 @@ static void disas_simd_indexed(DisasContext *s, ui=
nt32_t insn)
case 0x05: /* FMLS */
case 0x09: /* FMUL */
case 0x19: /* FMULX */
- if (size =3D=3D 1) {
- unallocated_encoding(s);
- return;
- }
is_fp =3D true;
break;
default:
@@ -11834,45 +11830,48 @@ static void disas_simd_indexed(DisasContext *s, u=
int32_t insn)
if (is_fp) {
/* convert insn encoded size to TCGMemOp size */
switch (size) {
- case 2: /* single precision */
- size =3D MO_32;
- index =3D h << 1 | l;
- rm |=3D (m << 4);
- break;
- case 3: /* double precision */
- size =3D MO_64;
- if (l || !is_q) {
+ case 0: /* half-precision */
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
- index =3D h;
- rm |=3D (m << 4);
- break;
- case 0: /* half precision */
size =3D MO_16;
- index =3D h << 2 | l << 1 | m;
- is_fp16 =3D true;
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
- break;
- }
- /* fallthru */
- default: /* unallocated */
- unallocated_encoding(s);
- return;
- }
- } else {
- switch (size) {
- case 1:
- index =3D h << 2 | l << 1 | m;
break;
- case 2:
- index =3D h << 1 | l;
- rm |=3D (m << 4);
+ case MO_32: /* single precision */
+ case MO_64: /* double precision */
break;
default:
unallocated_encoding(s);
return;
}
+ } else {
+ switch (size) {
+ case MO_8:
+ case MO_64:
+ unallocated_encoding(s);
+ return;
+ }
+ }
+
+ /* Given TCGMemOp size, adjust register and indexing. */
+ switch (size) {
+ case MO_16:
+ index =3D h << 2 | l << 1 | m;
+ break;
+ case MO_32:
+ index =3D h << 1 | l;
+ rm |=3D m << 4;
+ break;
+ case MO_64:
+ if (l || !is_q) {
+ unallocated_encoding(s);
+ return;
+ }
+ index =3D h;
+ rm |=3D m << 4;
+ break;
+ default:
+ g_assert_not_reached();
}
=20
if (!fp_access_check(s)) {
--=20
2.16.2