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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 2 Mar 2018 11:06:21 +0000
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Subject: [Qemu-devel] [PULL 20/39] hw/misc/iotkit-secctl: Add handling for
PPCs
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The IoTKit Security Controller includes various registers
that expose to software the controls for the Peripheral
Protection Controllers in the system. Implement these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180220180325.29818-17-peter.maydell@linaro.org
---
include/hw/misc/iotkit-secctl.h | 64 +++++++++-
hw/misc/iotkit-secctl.c | 270 ++++++++++++++++++++++++++++++++++++=
+---
2 files changed, 315 insertions(+), 19 deletions(-)
diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secct=
l.h
index 872f652f8d..ea3d62967f 100644
--- a/include/hw/misc/iotkit-secctl.h
+++ b/include/hw/misc/iotkit-secctl.h
@@ -16,6 +16,28 @@
* QEMU interface:
* + sysbus MMIO region 0 is the "secure privilege control block" registe=
rs
* + sysbus MMIO region 1 is the "non-secure privilege control block" reg=
isters
+ * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
+ * should RAZ/WI or bus error
+ * Controlling the 2 APB PPCs in the IoTKit:
+ * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
+ * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
+ * + named GPIO outputs apb_ppc{0,1}_irq_enable
+ * + named GPIO outputs apb_ppc{0,1}_irq_clear
+ * + named GPIO inputs apb_ppc{0,1}_irq_status
+ * Controlling each of the 4 expansion APB PPCs which a system using the I=
oTKit
+ * might provide:
+ * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
+ * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
+ * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
+ * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
+ * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
+ * Controlling each of the 4 expansion AHB PPCs which a system using the I=
oTKit
+ * might provide:
+ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
+ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
+ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
+ * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
+ * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
*/
=20
#ifndef IOTKIT_SECCTL_H
@@ -26,14 +48,52 @@
#define TYPE_IOTKIT_SECCTL "iotkit-secctl"
#define IOTKIT_SECCTL(obj) OBJECT_CHECK(IoTKitSecCtl, (obj), TYPE_IOTKIT_S=
ECCTL)
=20
-typedef struct IoTKitSecCtl {
+#define IOTS_APB_PPC0_NUM_PORTS 3
+#define IOTS_APB_PPC1_NUM_PORTS 1
+#define IOTS_PPC_NUM_PORTS 16
+#define IOTS_NUM_APB_PPC 2
+#define IOTS_NUM_APB_EXP_PPC 4
+#define IOTS_NUM_AHB_EXP_PPC 4
+
+typedef struct IoTKitSecCtl IoTKitSecCtl;
+
+/* State and IRQ lines relating to a PPC. For the
+ * PPCs in the IoTKit not all the IRQ lines are used.
+ */
+typedef struct IoTKitSecCtlPPC {
+ qemu_irq nonsec[IOTS_PPC_NUM_PORTS];
+ qemu_irq ap[IOTS_PPC_NUM_PORTS];
+ qemu_irq irq_enable;
+ qemu_irq irq_clear;
+
+ uint32_t ns;
+ uint32_t sp;
+ uint32_t nsp;
+
+ /* Number of ports actually present */
+ int numports;
+ /* Offset of this PPC's interrupt bits in SECPPCINTSTAT */
+ int irq_bit_offset;
+ IoTKitSecCtl *parent;
+} IoTKitSecCtlPPC;
+
+struct IoTKitSecCtl {
/*< private >*/
SysBusDevice parent_obj;
=20
/*< public >*/
+ qemu_irq sec_resp_cfg;
=20
MemoryRegion s_regs;
MemoryRegion ns_regs;
-} IoTKitSecCtl;
+
+ uint32_t secppcintstat;
+ uint32_t secppcinten;
+ uint32_t secrespcfg;
+
+ IoTKitSecCtlPPC apb[IOTS_NUM_APB_PPC];
+ IoTKitSecCtlPPC apbexp[IOTS_NUM_APB_EXP_PPC];
+ IoTKitSecCtlPPC ahbexp[IOTS_NUM_APB_EXP_PPC];
+};
=20
#endif
diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c
index d106de95d7..1093f2910f 100644
--- a/hw/misc/iotkit-secctl.c
+++ b/hw/misc/iotkit-secctl.c
@@ -92,12 +92,41 @@ static const uint8_t iotkit_secctl_ns_idregs[] =3D {
0x0d, 0xf0, 0x05, 0xb1,
};
=20
+/* The register sets for the various PPCs (AHB internal, APB internal,
+ * AHB expansion, APB expansion) are all set up so that they are
+ * in 16-aligned blocks so offsets 0xN0, 0xN4, 0xN8, 0xNC are PPCs
+ * 0, 1, 2, 3 of that type, so we can convert a register address offset
+ * into an an index into a PPC array easily.
+ */
+static inline int offset_to_ppc_idx(uint32_t offset)
+{
+ return extract32(offset, 2, 2);
+}
+
+typedef void PerPPCFunction(IoTKitSecCtlPPC *ppc);
+
+static void foreach_ppc(IoTKitSecCtl *s, PerPPCFunction *fn)
+{
+ int i;
+
+ for (i =3D 0; i < IOTS_NUM_APB_PPC; i++) {
+ fn(&s->apb[i]);
+ }
+ for (i =3D 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
+ fn(&s->apbexp[i]);
+ }
+ for (i =3D 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
+ fn(&s->ahbexp[i]);
+ }
+}
+
static MemTxResult iotkit_secctl_s_read(void *opaque, hwaddr addr,
uint64_t *pdata,
unsigned size, MemTxAttrs attrs)
{
uint64_t r;
uint32_t offset =3D addr & ~0x3;
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque);
=20
switch (offset) {
case A_AHBNSPPC0:
@@ -105,34 +134,52 @@ static MemTxResult iotkit_secctl_s_read(void *opaque,=
hwaddr addr,
r =3D 0;
break;
case A_SECRESPCFG:
- case A_NSCCFG:
- case A_SECMPCINTSTATUS:
+ r =3D s->secrespcfg;
+ break;
case A_SECPPCINTSTAT:
+ r =3D s->secppcintstat;
+ break;
case A_SECPPCINTEN:
- case A_SECMSCINTSTAT:
- case A_SECMSCINTEN:
- case A_BRGINTSTAT:
- case A_BRGINTEN:
+ r =3D s->secppcinten;
+ break;
case A_AHBNSPPCEXP0:
case A_AHBNSPPCEXP1:
case A_AHBNSPPCEXP2:
case A_AHBNSPPCEXP3:
+ r =3D s->ahbexp[offset_to_ppc_idx(offset)].ns;
+ break;
case A_APBNSPPC0:
case A_APBNSPPC1:
+ r =3D s->apb[offset_to_ppc_idx(offset)].ns;
+ break;
case A_APBNSPPCEXP0:
case A_APBNSPPCEXP1:
case A_APBNSPPCEXP2:
case A_APBNSPPCEXP3:
+ r =3D s->apbexp[offset_to_ppc_idx(offset)].ns;
+ break;
case A_AHBSPPPCEXP0:
case A_AHBSPPPCEXP1:
case A_AHBSPPPCEXP2:
case A_AHBSPPPCEXP3:
+ r =3D s->apbexp[offset_to_ppc_idx(offset)].sp;
+ break;
case A_APBSPPPC0:
case A_APBSPPPC1:
+ r =3D s->apb[offset_to_ppc_idx(offset)].sp;
+ break;
case A_APBSPPPCEXP0:
case A_APBSPPPCEXP1:
case A_APBSPPPCEXP2:
case A_APBSPPPCEXP3:
+ r =3D s->apbexp[offset_to_ppc_idx(offset)].sp;
+ break;
+ case A_NSCCFG:
+ case A_SECMPCINTSTATUS:
+ case A_SECMSCINTSTAT:
+ case A_SECMSCINTEN:
+ case A_BRGINTSTAT:
+ case A_BRGINTEN:
case A_NSMSCEXP:
qemu_log_mask(LOG_UNIMP,
"IoTKit SecCtl S block read: "
@@ -180,11 +227,66 @@ static MemTxResult iotkit_secctl_s_read(void *opaque,=
hwaddr addr,
return MEMTX_OK;
}
=20
+static void iotkit_secctl_update_ppc_ap(IoTKitSecCtlPPC *ppc)
+{
+ int i;
+
+ for (i =3D 0; i < ppc->numports; i++) {
+ bool v;
+
+ if (extract32(ppc->ns, i, 1)) {
+ v =3D extract32(ppc->nsp, i, 1);
+ } else {
+ v =3D extract32(ppc->sp, i, 1);
+ }
+ qemu_set_irq(ppc->ap[i], v);
+ }
+}
+
+static void iotkit_secctl_ppc_ns_write(IoTKitSecCtlPPC *ppc, uint32_t valu=
e)
+{
+ int i;
+
+ ppc->ns =3D value & MAKE_64BIT_MASK(0, ppc->numports);
+ for (i =3D 0; i < ppc->numports; i++) {
+ qemu_set_irq(ppc->nonsec[i], extract32(ppc->ns, i, 1));
+ }
+ iotkit_secctl_update_ppc_ap(ppc);
+}
+
+static void iotkit_secctl_ppc_sp_write(IoTKitSecCtlPPC *ppc, uint32_t valu=
e)
+{
+ ppc->sp =3D value & MAKE_64BIT_MASK(0, ppc->numports);
+ iotkit_secctl_update_ppc_ap(ppc);
+}
+
+static void iotkit_secctl_ppc_nsp_write(IoTKitSecCtlPPC *ppc, uint32_t val=
ue)
+{
+ ppc->nsp =3D value & MAKE_64BIT_MASK(0, ppc->numports);
+ iotkit_secctl_update_ppc_ap(ppc);
+}
+
+static void iotkit_secctl_ppc_update_irq_clear(IoTKitSecCtlPPC *ppc)
+{
+ uint32_t value =3D ppc->parent->secppcintstat;
+
+ qemu_set_irq(ppc->irq_clear, extract32(value, ppc->irq_bit_offset, 1));
+}
+
+static void iotkit_secctl_ppc_update_irq_enable(IoTKitSecCtlPPC *ppc)
+{
+ uint32_t value =3D ppc->parent->secppcinten;
+
+ qemu_set_irq(ppc->irq_enable, extract32(value, ppc->irq_bit_offset, 1)=
);
+}
+
static MemTxResult iotkit_secctl_s_write(void *opaque, hwaddr addr,
uint64_t value,
unsigned size, MemTxAttrs attrs)
{
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque);
uint32_t offset =3D addr;
+ IoTKitSecCtlPPC *ppc;
=20
trace_iotkit_secctl_s_write(offset, value, size);
=20
@@ -197,33 +299,61 @@ static MemTxResult iotkit_secctl_s_write(void *opaque=
, hwaddr addr,
=20
switch (offset) {
case A_SECRESPCFG:
- case A_NSCCFG:
+ value &=3D 1;
+ s->secrespcfg =3D value;
+ qemu_set_irq(s->sec_resp_cfg, s->secrespcfg);
+ break;
case A_SECPPCINTCLR:
+ value &=3D 0x00f000f3;
+ foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear);
+ break;
case A_SECPPCINTEN:
- case A_SECMSCINTCLR:
- case A_SECMSCINTEN:
- case A_BRGINTCLR:
- case A_BRGINTEN:
+ s->secppcinten =3D value & 0x00f000f3;
+ foreach_ppc(s, iotkit_secctl_ppc_update_irq_enable);
+ break;
case A_AHBNSPPCEXP0:
case A_AHBNSPPCEXP1:
case A_AHBNSPPCEXP2:
case A_AHBNSPPCEXP3:
+ ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_ns_write(ppc, value);
+ break;
case A_APBNSPPC0:
case A_APBNSPPC1:
+ ppc =3D &s->apb[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_ns_write(ppc, value);
+ break;
case A_APBNSPPCEXP0:
case A_APBNSPPCEXP1:
case A_APBNSPPCEXP2:
case A_APBNSPPCEXP3:
+ ppc =3D &s->apbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_ns_write(ppc, value);
+ break;
case A_AHBSPPPCEXP0:
case A_AHBSPPPCEXP1:
case A_AHBSPPPCEXP2:
case A_AHBSPPPCEXP3:
+ ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_sp_write(ppc, value);
+ break;
case A_APBSPPPC0:
case A_APBSPPPC1:
+ ppc =3D &s->apb[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_sp_write(ppc, value);
+ break;
case A_APBSPPPCEXP0:
case A_APBSPPPCEXP1:
case A_APBSPPPCEXP2:
case A_APBSPPPCEXP3:
+ ppc =3D &s->apbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_sp_write(ppc, value);
+ break;
+ case A_NSCCFG:
+ case A_SECMSCINTCLR:
+ case A_SECMSCINTEN:
+ case A_BRGINTCLR:
+ case A_BRGINTEN:
qemu_log_mask(LOG_UNIMP,
"IoTKit SecCtl S block write: "
"unimplemented offset 0x%x\n", offset);
@@ -265,6 +395,7 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque, =
hwaddr addr,
uint64_t *pdata,
unsigned size, MemTxAttrs attrs)
{
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque);
uint64_t r;
uint32_t offset =3D addr & ~0x3;
=20
@@ -276,15 +407,17 @@ static MemTxResult iotkit_secctl_ns_read(void *opaque=
, hwaddr addr,
case A_AHBNSPPPCEXP1:
case A_AHBNSPPPCEXP2:
case A_AHBNSPPPCEXP3:
+ r =3D s->ahbexp[offset_to_ppc_idx(offset)].nsp;
+ break;
case A_APBNSPPPC0:
case A_APBNSPPPC1:
+ r =3D s->apb[offset_to_ppc_idx(offset)].nsp;
+ break;
case A_APBNSPPPCEXP0:
case A_APBNSPPPCEXP1:
case A_APBNSPPPCEXP2:
case A_APBNSPPPCEXP3:
- qemu_log_mask(LOG_UNIMP,
- "IoTKit SecCtl NS block read: "
- "unimplemented offset 0x%x\n", offset);
+ r =3D s->apbexp[offset_to_ppc_idx(offset)].nsp;
break;
case A_PID4:
case A_PID5:
@@ -324,7 +457,9 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque,=
hwaddr addr,
uint64_t value,
unsigned size, MemTxAttrs attrs)
{
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(opaque);
uint32_t offset =3D addr;
+ IoTKitSecCtlPPC *ppc;
=20
trace_iotkit_secctl_ns_write(offset, value, size);
=20
@@ -340,15 +475,20 @@ static MemTxResult iotkit_secctl_ns_write(void *opaqu=
e, hwaddr addr,
case A_AHBNSPPPCEXP1:
case A_AHBNSPPPCEXP2:
case A_AHBNSPPPCEXP3:
+ ppc =3D &s->ahbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_nsp_write(ppc, value);
+ break;
case A_APBNSPPPC0:
case A_APBNSPPPC1:
+ ppc =3D &s->apb[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_nsp_write(ppc, value);
+ break;
case A_APBNSPPPCEXP0:
case A_APBNSPPPCEXP1:
case A_APBNSPPPCEXP2:
case A_APBNSPPPCEXP3:
- qemu_log_mask(LOG_UNIMP,
- "IoTKit SecCtl NS block write: "
- "unimplemented offset 0x%x\n", offset);
+ ppc =3D &s->apbexp[offset_to_ppc_idx(offset)];
+ iotkit_secctl_ppc_nsp_write(ppc, value);
break;
case A_AHBNSPPPC0:
case A_PID4:
@@ -397,15 +537,90 @@ static const MemoryRegionOps iotkit_secctl_ns_ops =3D=
{
.impl.max_access_size =3D 4,
};
=20
+static void iotkit_secctl_reset_ppc(IoTKitSecCtlPPC *ppc)
+{
+ ppc->ns =3D 0;
+ ppc->sp =3D 0;
+ ppc->nsp =3D 0;
+}
+
static void iotkit_secctl_reset(DeviceState *dev)
{
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(dev);
=20
+ s->secppcintstat =3D 0;
+ s->secppcinten =3D 0;
+ s->secrespcfg =3D 0;
+
+ foreach_ppc(s, iotkit_secctl_reset_ppc);
+}
+
+static void iotkit_secctl_ppc_irqstatus(void *opaque, int n, int level)
+{
+ IoTKitSecCtlPPC *ppc =3D opaque;
+ IoTKitSecCtl *s =3D IOTKIT_SECCTL(ppc->parent);
+ int irqbit =3D ppc->irq_bit_offset + n;
+
+ s->secppcintstat =3D deposit32(s->secppcintstat, irqbit, 1, level);
+}
+
+static void iotkit_secctl_init_ppc(IoTKitSecCtl *s,
+ IoTKitSecCtlPPC *ppc,
+ const char *name,
+ int numports,
+ int irq_bit_offset)
+{
+ char *gpioname;
+ DeviceState *dev =3D DEVICE(s);
+
+ ppc->numports =3D numports;
+ ppc->irq_bit_offset =3D irq_bit_offset;
+ ppc->parent =3D s;
+
+ gpioname =3D g_strdup_printf("%s_nonsec", name);
+ qdev_init_gpio_out_named(dev, ppc->nonsec, gpioname, numports);
+ g_free(gpioname);
+ gpioname =3D g_strdup_printf("%s_ap", name);
+ qdev_init_gpio_out_named(dev, ppc->ap, gpioname, numports);
+ g_free(gpioname);
+ gpioname =3D g_strdup_printf("%s_irq_enable", name);
+ qdev_init_gpio_out_named(dev, &ppc->irq_enable, gpioname, 1);
+ g_free(gpioname);
+ gpioname =3D g_strdup_printf("%s_irq_clear", name);
+ qdev_init_gpio_out_named(dev, &ppc->irq_clear, gpioname, 1);
+ g_free(gpioname);
+ gpioname =3D g_strdup_printf("%s_irq_status", name);
+ qdev_init_gpio_in_named_with_opaque(dev, iotkit_secctl_ppc_irqstatus,
+ ppc, gpioname, 1);
+ g_free(gpioname);
}
=20
static void iotkit_secctl_init(Object *obj)
{
IoTKitSecCtl *s =3D IOTKIT_SECCTL(obj);
SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ DeviceState *dev =3D DEVICE(obj);
+ int i;
+
+ iotkit_secctl_init_ppc(s, &s->apb[0], "apb_ppc0",
+ IOTS_APB_PPC0_NUM_PORTS, 0);
+ iotkit_secctl_init_ppc(s, &s->apb[1], "apb_ppc1",
+ IOTS_APB_PPC1_NUM_PORTS, 1);
+
+ for (i =3D 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
+ IoTKitSecCtlPPC *ppc =3D &s->apbexp[i];
+ char *ppcname =3D g_strdup_printf("apb_ppcexp%d", i);
+ iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 4 + i);
+ g_free(ppcname);
+ }
+ for (i =3D 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
+ IoTKitSecCtlPPC *ppc =3D &s->ahbexp[i];
+ char *ppcname =3D g_strdup_printf("ahb_ppcexp%d", i);
+ iotkit_secctl_init_ppc(s, ppc, ppcname, IOTS_PPC_NUM_PORTS, 20 + i=
);
+ g_free(ppcname);
+ }
+
+ qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1);
=20
memory_region_init_io(&s->s_regs, obj, &iotkit_secctl_s_ops,
s, "iotkit-secctl-s-regs", 0x1000);
@@ -415,11 +630,32 @@ static void iotkit_secctl_init(Object *obj)
sysbus_init_mmio(sbd, &s->ns_regs);
}
=20
+static const VMStateDescription iotkit_secctl_ppc_vmstate =3D {
+ .name =3D "iotkit-secctl-ppc",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32(ns, IoTKitSecCtlPPC),
+ VMSTATE_UINT32(sp, IoTKitSecCtlPPC),
+ VMSTATE_UINT32(nsp, IoTKitSecCtlPPC),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription iotkit_secctl_vmstate =3D {
.name =3D "iotkit-secctl",
.version_id =3D 1,
.minimum_version_id =3D 1,
.fields =3D (VMStateField[]) {
+ VMSTATE_UINT32(secppcintstat, IoTKitSecCtl),
+ VMSTATE_UINT32(secppcinten, IoTKitSecCtl),
+ VMSTATE_UINT32(secrespcfg, IoTKitSecCtl),
+ VMSTATE_STRUCT_ARRAY(apb, IoTKitSecCtl, IOTS_NUM_APB_PPC, 1,
+ iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
+ VMSTATE_STRUCT_ARRAY(apbexp, IoTKitSecCtl, IOTS_NUM_APB_EXP_PPC, 1,
+ iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
+ VMSTATE_STRUCT_ARRAY(ahbexp, IoTKitSecCtl, IOTS_NUM_AHB_EXP_PPC, 1,
+ iotkit_secctl_ppc_vmstate, IoTKitSecCtlPPC),
VMSTATE_END_OF_LIST()
}
};
--=20
2.16.2