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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 2 Mar 2018 11:06:11 +0000
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Subject: [Qemu-devel] [PULL 10/39] target/arm: Define init-svtor property
for the reset secure VTOR value
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The Cortex-M33 allows the system to specify the reset value of the
secure Vector Table Offset Register (VTOR) by asserting config
signals. In particular, guest images for the MPS2 AN505 board rely
on the MPS2's initial VTOR being correct for that board.
Implement a QEMU property so board and SoC code can set the reset
value to the correct value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180220180325.29818-7-peter.maydell@linaro.org
---
target/arm/cpu.h | 3 +++
target/arm/cpu.c | 18 ++++++++++++++----
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4710a43110..72b5668377 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -731,6 +731,9 @@ struct ARMCPU {
*/
uint32_t psci_conduit;
=20
+ /* For v8M, initial value of the Secure VTOR */
+ uint32_t init_svtor;
+
/* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
* QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU typ=
e.
*/
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 291ff0b1db..27d9e90308 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -187,6 +187,7 @@ static void arm_cpu_reset(CPUState *s)
uint32_t initial_msp; /* Loaded from 0x0 */
uint32_t initial_pc; /* Loaded from 0x4 */
uint8_t *rom;
+ uint32_t vecbase;
=20
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
env->v7m.secure =3D true;
@@ -214,8 +215,11 @@ static void arm_cpu_reset(CPUState *s)
/* Unlike A/R profile, M profile defines the reset LR value */
env->regs[14] =3D 0xffffffff;
=20
- /* Load the initial SP and PC from the vector table at address 0 */
- rom =3D rom_ptr(0);
+ env->v7m.vecbase[M_REG_S] =3D cpu->init_svtor & 0xffffff80;
+
+ /* Load the initial SP and PC from offset 0 and 4 in the vector ta=
ble */
+ vecbase =3D env->v7m.vecbase[env->v7m.secure];
+ rom =3D rom_ptr(vecbase);
if (rom) {
/* Address zero is covered by ROM which hasn't yet been
* copied into physical memory.
@@ -228,8 +232,8 @@ static void arm_cpu_reset(CPUState *s)
* it got copied into memory. In the latter case, rom_ptr
* will return a NULL pointer and we should use ldl_phys inste=
ad.
*/
- initial_msp =3D ldl_phys(s->as, 0);
- initial_pc =3D ldl_phys(s->as, 4);
+ initial_msp =3D ldl_phys(s->as, vecbase);
+ initial_pc =3D ldl_phys(s->as, vecbase + 4);
}
=20
env->regs[13] =3D initial_msp & 0xFFFFFFFC;
@@ -624,6 +628,10 @@ static Property arm_cpu_pmsav7_dregion_property =3D
pmsav7_dregion,
qdev_prop_uint32, uint32_t);
=20
+/* M profile: initial value of the Secure VTOR */
+static Property arm_cpu_initsvtor_property =3D
+ DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
+
static void arm_cpu_post_init(Object *obj)
{
ARMCPU *cpu =3D ARM_CPU(obj);
@@ -694,6 +702,8 @@ static void arm_cpu_post_init(Object *obj)
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
+ &error_abort);
}
=20
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
--=20
2.16.2