From nobody Wed Oct 22 13:02:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519910589137246.72082923975017; Thu, 1 Mar 2018 05:23:09 -0800 (PST) Received: from localhost ([::1]:56446 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erOAu-0004f6-4M for importer@patchew.org; Thu, 01 Mar 2018 08:23:08 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58801) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erNrP-0004IW-Qs for qemu-devel@nongnu.org; Thu, 01 Mar 2018 08:03:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erNrO-0007Rv-UQ for qemu-devel@nongnu.org; Thu, 01 Mar 2018 08:02:59 -0500 Received: from mx3-rdu2.redhat.com ([66.187.233.73]:43434 helo=mx1.redhat.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erNrO-0007RV-QB; Thu, 01 Mar 2018 08:02:58 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5A974402676F; Thu, 1 Mar 2018 13:02:58 +0000 (UTC) Received: from localhost (ovpn-117-50.ams2.redhat.com [10.36.117.50]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BF3779C044; Thu, 1 Mar 2018 13:02:55 +0000 (UTC) From: Cornelia Huck To: peter.maydell@linaro.org Date: Thu, 1 Mar 2018 14:01:51 +0100 Message-Id: <20180301130201.24666-18-cohuck@redhat.com> In-Reply-To: <20180301130201.24666-1-cohuck@redhat.com> References: <20180301130201.24666-1-cohuck@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.11.54.5 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Thu, 01 Mar 2018 13:02:58 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.6]); Thu, 01 Mar 2018 13:02:58 +0000 (UTC) for IP:'10.11.54.5' DOMAIN:'int-mx05.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'cohuck@redhat.com' RCPT:'' X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.187.233.73 Subject: [Qemu-devel] [PULL v2 17/27] s390x/tcg: fix disabling/enabling DAT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, Cornelia Huck , qemu-devel@nongnu.org, agraf@suse.de, borntraeger@de.ibm.com, qemu-s390x@nongnu.org, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: David Hildenbrand Currently, all memory accesses go via the MMU of the address space (primary, secondary, ...). This is bad, because we don't flush the TLB when disabling/enabling DAT. So we could add a tlb flush. However it is easier to simply select the MMU we already have in place for real memory access. All we have to do is point at the right MMU and allow to execute these pages. Signed-off-by: David Hildenbrand Message-Id: <20180213161240.19891-1-david@redhat.com> Reviewed-by: Richard Henderson [CH: get rid of tabs] Signed-off-by: Cornelia Huck --- target/s390x/cpu.h | 7 ++++++- target/s390x/mmu_helper.c | 2 +- target/s390x/translate.c | 10 +++++++--- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 09ec8a9b76..d4641663ef 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -312,11 +312,12 @@ extern const struct VMStateDescription vmstate_s390_c= pu; =20 #define FLAG_MASK_PSW_SHIFT 31 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) +#define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) -#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \ +#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK= _PSTATE \ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK= _32) =20 /* Control register 0 bits */ @@ -340,6 +341,10 @@ extern const struct VMStateDescription vmstate_s390_cp= u; =20 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) { + if (!(env->psw.mask & PSW_MASK_DAT)) { + return MMU_REAL_IDX; + } + switch (env->psw.mask & PSW_MASK_ASC) { case PSW_ASC_PRIMARY: return MMU_PRIMARY_IDX; diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index f477cc006a..23fb2e7501 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -544,7 +544,7 @@ int mmu_translate_real(CPUS390XState *env, target_ulong= raddr, int rw, { const bool lowprot_enabled =3D env->cregs[0] & CR0_LOWPROT; =20 - *flags =3D PAGE_READ | PAGE_WRITE; + *flags =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) { /* see comment in mmu_translate() how this works */ *flags |=3D PAGE_WRITE_INV; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index b470d691d3..5aea3bbca6 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -252,13 +252,17 @@ static inline uint64_t ld_code4(CPUS390XState *env, u= int64_t pc) =20 static int get_mem_index(DisasContext *s) { + if (!(s->tb->flags & FLAG_MASK_DAT)) { + return MMU_REAL_IDX; + } + switch (s->tb->flags & FLAG_MASK_ASC) { case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT: - return 0; + return MMU_PRIMARY_IDX; case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT: - return 1; + return MMU_SECONDARY_IDX; case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT: - return 2; + return MMU_HOME_IDX; default: tcg_abort(); break; --=20 2.13.6