From nobody Fri Dec 19 04:32:17 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519905367626873.6188035617052; Thu, 1 Mar 2018 03:56:07 -0800 (PST) Received: from localhost ([::1]:55883 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMob-0002Mu-BN for importer@patchew.org; Thu, 01 Mar 2018 06:56:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMK7-0003xH-QY for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMK6-0008EN-20 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:31 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMK5-0008Du-NI for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:29 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMK4-0000g2-Kj for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:28 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:55 +0000 Message-Id: <20180301112403.12487-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-27-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/helper.c | 221 ++++++++++++++++++++++++------------------------= ---- 2 files changed, 104 insertions(+), 118 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 81d7baed6d..6dd8504ec3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -195,6 +195,7 @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(recpe_u32, i32, i32, ptr) diff --git a/target/arm/helper.c b/target/arm/helper.c index e2d0ff0b4c..c82f63d440 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11756,56 +11756,97 @@ float64 HELPER(recpe_f64)(float64 input, void *fp= stp) /* The algorithm that must be used to calculate the estimate * is specified by the ARM ARM. */ -static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) + +static int do_recip_sqrt_estimate(int a) { - /* These calculations mustn't set any fp exception flags, - * so we use a local copy of the fp_status. - */ - float_status dummy_status =3D *real_fp_status; - float_status *s =3D &dummy_status; - float64 q; - int64_t q_int; + int b, estimate; =20 - if (float64_lt(a, float64_half, s)) { - /* range 0.25 <=3D a < 0.5 */ - - /* a in units of 1/512 rounded down */ - /* q0 =3D (int)(a * 512.0); */ - q =3D float64_mul(float64_512, a, s); - q_int =3D float64_to_int64_round_to_zero(q, s); - - /* reciprocal root r */ - /* r =3D 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ - q =3D int64_to_float64(q_int, s); - q =3D float64_add(q, float64_half, s); - q =3D float64_div(q, float64_512, s); - q =3D float64_sqrt(q, s); - q =3D float64_div(float64_one, q, s); + assert(128 <=3D a && a < 512); + if (a < 256) { + a =3D a * 2 + 1; } else { - /* range 0.5 <=3D a < 1.0 */ - - /* a in units of 1/256 rounded down */ - /* q1 =3D (int)(a * 256.0); */ - q =3D float64_mul(float64_256, a, s); - int64_t q_int =3D float64_to_int64_round_to_zero(q, s); - - /* reciprocal root r */ - /* r =3D 1.0 /sqrt(((double)q1 + 0.5) / 256); */ - q =3D int64_to_float64(q_int, s); - q =3D float64_add(q, float64_half, s); - q =3D float64_div(q, float64_256, s); - q =3D float64_sqrt(q, s); - q =3D float64_div(float64_one, q, s); + a =3D (a >> 1) << 1; + a =3D (a + 1) * 2; } - /* r in units of 1/256 rounded to nearest */ - /* s =3D (int)(256.0 * r + 0.5); */ + b =3D 512; + while (a * (b + 1) * (b + 1) < (1 << 28)) { + b +=3D 1; + } + estimate =3D (b + 1) / 2; + assert(256 <=3D estimate && estimate < 512); =20 - q =3D float64_mul(q, float64_256,s ); - q =3D float64_add(q, float64_half, s); - q_int =3D float64_to_int64_round_to_zero(q, s); + return estimate; +} =20 - /* return (double)s / 256.0;*/ - return float64_div(int64_to_float64(q_int, s), float64_256, s); + +static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) +{ + int estimate; + uint32_t scaled; + + if (*exp =3D=3D 0) { + while (extract64(frac, 51, 1) =3D=3D 0) { + frac =3D frac << 1; + *exp -=3D 1; + } + frac =3D extract64(frac, 0, 51) << 1; + } + + if (*exp & 1) { + /* scaled =3D UInt('01':fraction<51:45>) */ + scaled =3D deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); + } else { + /* scaled =3D UInt('1':fraction<51:44>) */ + scaled =3D deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); + } + estimate =3D do_recip_sqrt_estimate(scaled); + + *exp =3D (exp_off - *exp) / 2; + return extract64(estimate, 0, 8) << 44; +} + +float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) +{ + float_status *s =3D fpstp; + float16 f16 =3D float16_squash_input_denormal(input, s); + uint16_t val =3D float16_val(f16); + bool f16_sign =3D float16_is_neg(f16); + int f16_exp =3D extract32(val, 10, 5); + uint16_t f16_frac =3D extract32(val, 0, 10); + uint64_t f64_frac; + + if (float16_is_any_nan(f16)) { + float16 nan =3D f16; + if (float16_is_signaling_nan(f16, s)) { + float_raise(float_flag_invalid, s); + nan =3D float16_maybe_silence_nan(f16, s); + } + if (s->default_nan_mode) { + nan =3D float16_default_nan(s); + } + return nan; + } else if (float16_is_zero(f16)) { + float_raise(float_flag_divbyzero, s); + return float16_set_sign(float16_infinity, f16_sign); + } else if (f16_sign) { + float_raise(float_flag_invalid, s); + return float16_default_nan(s); + } else if (float16_is_infinity(f16)) { + return float16_zero; + } + + /* Scale and normalize to a double-precision value between 0.25 and 1.= 0, + * preserving the parity of the exponent. */ + + f64_frac =3D ((uint64_t) f16_frac) << (52 - 10); + + f64_frac =3D recip_sqrt_estimate(&f16_exp, 44, f64_frac); + + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ + val =3D deposit32(0, 15, 1, f16_sign); + val =3D deposit32(val, 10, 5, f16_exp); + val =3D deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float16(val); } =20 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) @@ -11813,13 +11854,10 @@ float32 HELPER(rsqrte_f32)(float32 input, void *f= pstp) float_status *s =3D fpstp; float32 f32 =3D float32_squash_input_denormal(input, s); uint32_t val =3D float32_val(f32); - uint32_t f32_sbit =3D 0x80000000 & val; - int32_t f32_exp =3D extract32(val, 23, 8); + uint32_t f32_sign =3D float32_is_neg(f32); + int f32_exp =3D extract32(val, 23, 8); uint32_t f32_frac =3D extract32(val, 0, 23); uint64_t f64_frac; - uint64_t val64; - int result_exp; - float64 f64; =20 if (float32_is_any_nan(f32)) { float32 nan =3D f32; @@ -11845,32 +11883,13 @@ float32 HELPER(rsqrte_f32)(float32 input, void *f= pstp) * preserving the parity of the exponent. */ =20 f64_frac =3D ((uint64_t) f32_frac) << 29; - if (f32_exp =3D=3D 0) { - while (extract64(f64_frac, 51, 1) =3D=3D 0) { - f64_frac =3D f64_frac << 1; - f32_exp =3D f32_exp-1; - } - f64_frac =3D extract64(f64_frac, 0, 51) << 1; - } =20 - if (extract64(f32_exp, 0, 1) =3D=3D 0) { - f64 =3D make_float64(((uint64_t) f32_sbit) << 32 - | (0x3feULL << 52) - | f64_frac); - } else { - f64 =3D make_float64(((uint64_t) f32_sbit) << 32 - | (0x3fdULL << 52) - | f64_frac); - } + f64_frac =3D recip_sqrt_estimate(&f32_exp, 380, f64_frac); =20 - result_exp =3D (380 - f32_exp) / 2; - - f64 =3D recip_sqrt_estimate(f64, s); - - val64 =3D float64_val(f64); - - val =3D ((result_exp & 0xff) << 23) - | ((val64 >> 29) & 0x7fffff); + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ + val =3D deposit32(0, 31, 1, f32_sign); + val =3D deposit32(val, 23, 8, f32_exp); + val =3D deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); return make_float32(val); } =20 @@ -11879,11 +11898,9 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fp= stp) float_status *s =3D fpstp; float64 f64 =3D float64_squash_input_denormal(input, s); uint64_t val =3D float64_val(f64); - uint64_t f64_sbit =3D 0x8000000000000000ULL & val; - int64_t f64_exp =3D extract64(val, 52, 11); + bool f64_sign =3D float64_is_neg(f64); + int f64_exp =3D extract64(val, 52, 11); uint64_t f64_frac =3D extract64(val, 0, 52); - int64_t result_exp; - uint64_t result_frac; =20 if (float64_is_any_nan(f64)) { float64 nan =3D f64; @@ -11905,36 +11922,13 @@ float64 HELPER(rsqrte_f64)(float64 input, void *f= pstp) return float64_zero; } =20 - /* Scale and normalize to a double-precision value between 0.25 and 1.= 0, - * preserving the parity of the exponent. */ + f64_frac =3D recip_sqrt_estimate(&f64_exp, 3068, f64_frac); =20 - if (f64_exp =3D=3D 0) { - while (extract64(f64_frac, 51, 1) =3D=3D 0) { - f64_frac =3D f64_frac << 1; - f64_exp =3D f64_exp - 1; - } - f64_frac =3D extract64(f64_frac, 0, 51) << 1; - } - - if (extract64(f64_exp, 0, 1) =3D=3D 0) { - f64 =3D make_float64(f64_sbit - | (0x3feULL << 52) - | f64_frac); - } else { - f64 =3D make_float64(f64_sbit - | (0x3fdULL << 52) - | f64_frac); - } - - result_exp =3D (3068 - f64_exp) / 2; - - f64 =3D recip_sqrt_estimate(f64, s); - - result_frac =3D extract64(float64_val(f64), 0, 52); - - return make_float64(f64_sbit | - ((result_exp & 0x7ff) << 52) | - result_frac); + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ + val =3D deposit64(0, 61, 1, f64_sign); + val =3D deposit64(val, 52, 11, f64_exp); + val =3D deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float64(val); } =20 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) @@ -11954,24 +11948,15 @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpst= p) =20 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) { - float_status *fpst =3D fpstp; - float64 f64; + int estimate; =20 if ((a & 0xc0000000) =3D=3D 0) { return 0xffffffff; } =20 - if (a & 0x80000000) { - f64 =3D make_float64((0x3feULL << 52) - | ((uint64_t)(a & 0x7fffffff) << 21)); - } else { /* bits 31-30 =3D=3D '01' */ - f64 =3D make_float64((0x3fdULL << 52) - | ((uint64_t)(a & 0x3fffffff) << 22)); - } + estimate =3D do_recip_sqrt_estimate(extract32(a, 23, 9)); =20 - f64 =3D recip_sqrt_estimate(f64, fpst); - - return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); + return deposit32(0, 23, 9, estimate); } =20 /* VFPv4 fused multiply-accumulate */ --=20 2.16.2