From nobody Thu Dec 18 22:26:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519906100889284.74997822363036; Thu, 1 Mar 2018 04:08:20 -0800 (PST) Received: from localhost ([::1]:55848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMie-0006AA-6v for importer@patchew.org; Thu, 01 Mar 2018 06:49:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMK5-0003uG-EJ for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMK4-0008Dl-BG for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:29 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46720) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMK4-0008DQ-4t for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:28 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMK3-0000fQ-87 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:53 +0000 Message-Id: <20180301112403.12487-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 32/42] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e We go with the localised helper. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-25-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 1 + target/arm/helper-a64.c | 29 +++++++++++++++++++++++++++++ target/arm/translate-a64.c | 4 ++++ 3 files changed, 34 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 32931b17c6..339323fc3d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -41,6 +41,7 @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i6= 4, i64) DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 722fff2349..92a0d55a9c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -356,6 +356,35 @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a) } =20 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ +float16 HELPER(frecpx_f16)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + uint16_t val16, sbit; + int16_t exp; + + if (float16_is_any_nan(a)) { + float16 nan =3D a; + if (float16_is_signaling_nan(a, fpst)) { + float_raise(float_flag_invalid, fpst); + nan =3D float16_maybe_silence_nan(a, fpst); + } + if (fpst->default_nan_mode) { + nan =3D float16_default_nan(fpst); + } + return nan; + } + + val16 =3D float16_val(a); + sbit =3D 0x8000 & val16; + exp =3D extract32(val16, 10, 5); + + if (exp =3D=3D 0) { + return make_float16(deposit32(sbit, 10, 5, 0x1e)); + } else { + return make_float16(deposit32(sbit, 10, 5, ~exp)); + } +} + float32 HELPER(frecpx_f32)(float32 a, void *fpstp) { float_status *fpst =3D fpstp; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 50b4fa4ce4..715dc4333d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11312,6 +11312,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; case 0x3d: /* FRECPE */ + case 0x3f: /* FRECPX */ break; case 0x18: /* FRINTN */ need_rmode =3D true; @@ -11436,6 +11437,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x3d: /* FRECPE */ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3f: /* FRECPX */ + gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ --=20 2.16.2