From nobody Thu Dec 18 22:21:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519904731789897.7707386643077; Thu, 1 Mar 2018 03:45:31 -0800 (PST) Received: from localhost ([::1]:55813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMdm-0004Et-04 for importer@patchew.org; Thu, 01 Mar 2018 06:44:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33972) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMK3-0003sN-DH for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMK2-0008Cu-Hi for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMK2-0008CG-Aq for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:26 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMK1-0000eg-3n for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:50 +0000 Message-Id: <20180301112403.12487-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 29/42] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-22-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6f33783a11..9f2c3682dc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) TCGv_i32 tcg_rmode =3D NULL; TCGv_ptr tcg_fpstatus =3D NULL; bool need_rmode =3D false; + bool need_fpst =3D true; int rmode; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { @@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) need_rmode =3D true; rmode =3D FPROUNDING_ZERO; break; + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + need_fpst =3D false; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) return; } =20 - if (need_rmode) { + if (need_rmode || need_fpst) { tcg_fpstatus =3D get_fpstatus_ptr(true); } =20 @@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } @@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) case 0x59: /* FRINTX */ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstat= us); break; + case 0x2f: /* FABS */ + tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); + break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } --=20 2.16.2