From nobody Thu Dec 18 19:32:56 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 151990373857826.066454436796562; Thu, 1 Mar 2018 03:28:58 -0800 (PST) Received: from localhost ([::1]:55731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMOP-0007i8-Ii for importer@patchew.org; Thu, 01 Mar 2018 06:28:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMJv-0003is-9z for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJu-00087T-6w for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:19 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46698) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJt-00082m-U8 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:18 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJh-0000XZ-Us for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:23 +0000 Message-Id: <20180301112403.12487-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Francisco Iglesias Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and chip selects are enabled (e.g reading/writing with stripe). Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Tested-by: Alistair Francis Message-id: 20180223232233.31482-2-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8af36ca3d4..0cb484ecf4 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -223,7 +223,7 @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int = field) { int i; =20 - for (i =3D 0; i < s->num_cs; i++) { + for (i =3D 0; i < s->num_cs * s->num_busses; i++) { bool old_state =3D s->cs_lines_state[i]; bool new_state =3D field & (1 << i); =20 @@ -234,7 +234,7 @@ static void xilinx_spips_update_cs(XilinxSPIPS *s, int = field) } qemu_set_irq(s->cs_lines[i], !new_state); } - if (!(field & ((1 << s->num_cs) - 1))) { + if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { s->snoop_state =3D SNOOP_CHECKING; s->cmd_dummies =3D 0; s->link_state =3D 1; @@ -248,7 +248,40 @@ static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZyn= qMPQSPIPS *s) { if (s->regs[R_GQSPI_GF_SNAPSHOT]) { int field =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SE= LECT); - xilinx_spips_update_cs(XILINX_SPIPS(s), field); + bool upper_cs_sel =3D field & (1 << 1); + bool lower_cs_sel =3D field & 1; + bool bus0_enabled; + bool bus1_enabled; + uint8_t buses; + int cs =3D 0; + + buses =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SE= LECT); + bus0_enabled =3D buses & 1; + bus1_enabled =3D buses & (1 << 1); + + if (bus0_enabled && bus1_enabled) { + if (lower_cs_sel) { + cs |=3D 1; + } + if (upper_cs_sel) { + cs |=3D 1 << 3; + } + } else if (bus0_enabled) { + if (lower_cs_sel) { + cs |=3D 1; + } + if (upper_cs_sel) { + cs |=3D 1 << 1; + } + } else if (bus1_enabled) { + if (lower_cs_sel) { + cs |=3D 1 << 2; + } + if (upper_cs_sel) { + cs |=3D 1 << 3; + } + } + xilinx_spips_update_cs(XILINX_SPIPS(s), cs); } } =20 @@ -260,7 +293,7 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) if (num_effective_busses(s) =3D=3D 2) { /* Single bit chip-select for qspi */ field &=3D 0x1; - field |=3D field << 1; + field |=3D field << 3; /* Dual stack U-Page */ } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { --=20 2.16.2