From nobody Thu Dec 18 19:34:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519904290454820.1656841581594; Thu, 1 Mar 2018 03:38:10 -0800 (PST) Received: from localhost ([::1]:55778 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMX5-0006wM-24 for importer@patchew.org; Thu, 01 Mar 2018 06:37:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMK0-0003oy-Vf for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJz-0008BZ-LQ for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:24 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46712) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJz-0008AR-CA for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:23 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJy-0000df-A7 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:22 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:46 +0000 Message-Id: <20180301112403.12487-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-18-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 2 + target/arm/helper-a64.c | 22 ++++++++ target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++= ++-- 3 files changed, 142 insertions(+), 5 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 003ffa582f..bc8d5b105b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -75,3 +75,5 @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) +DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4d5ae96d8f..4fd28fdf48 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -745,3 +745,25 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b= , void *fpstp) int compare =3D float16_compare(f0, f1, fpst); return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); } + +/* round to integral */ +float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status) +{ + return float16_round_to_int(x, fp_status); +} + +float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) +{ + int old_flags =3D get_float_exception_flags(fp_status), new_flags; + float16 ret; + + ret =3D float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags =3D get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_stat= us); + } + + return ret; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c1892c49a..3c37eb99ff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11180,27 +11180,140 @@ static void disas_simd_two_reg_misc(DisasContext= *s, uint32_t insn) */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { - int fpop, opcode, a; + int fpop, opcode, a, u; + int rn, rd; + bool is_q; + bool is_scalar; + bool only_in_vector =3D false; + + int pass; + TCGv_i32 tcg_rmode =3D NULL; + TCGv_ptr tcg_fpstatus =3D NULL; + bool need_rmode =3D false; + int rmode; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } =20 - if (!fp_access_check(s)) { - return; - } + rd =3D extract32(insn, 0, 5); + rn =3D extract32(insn, 5, 5); =20 - opcode =3D extract32(insn, 12, 4); a =3D extract32(insn, 23, 1); + u =3D extract32(insn, 29, 1); + is_scalar =3D extract32(insn, 28, 1); + is_q =3D extract32(insn, 30, 1); + + opcode =3D extract32(insn, 12, 5); fpop =3D deposit32(opcode, 5, 1, a); + fpop =3D deposit32(fpop, 6, 1, u); =20 switch (fpop) { + case 0x18: /* FRINTN */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x19: /* FRINTM */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x38: /* FRINTP */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x39: /* FRINTZ */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_ZERO; + break; + case 0x58: /* FRINTA */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x59: /* FRINTX */ + case 0x79: /* FRINTI */ + only_in_vector =3D true; + /* current rounding mode */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); } =20 + + /* Check additional constraints for the scalar encoding */ + if (is_scalar) { + if (!is_q) { + unallocated_encoding(s); + return; + } + /* FRINTxx is only in the vector form */ + if (only_in_vector) { + unallocated_encoding(s); + return; + } + } + + if (!fp_access_check(s)) { + return; + } + + if (need_rmode) { + tcg_fpstatus =3D get_fpstatus_ptr(true); + } + + if (need_rmode) { + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + } + + if (is_scalar) { + /* no operations yet */ + } else { + for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_16); + + switch (fpop) { + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + case 0x58: /* FRINTA */ + case 0x79: /* FRINTI */ + gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x59: /* FRINTX */ + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstat= us); + break; + default: + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + } + + clear_vec_high(s, is_q, rd); + } + + if (tcg_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_temp_free_i32(tcg_rmode); + } + + if (tcg_fpstatus) { + tcg_temp_free_ptr(tcg_fpstatus); + } } =20 /* AdvSIMD scalar x indexed element --=20 2.16.2