From nobody Thu Dec 18 22:20:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519903907673479.45118243822606; Thu, 1 Mar 2018 03:31:47 -0800 (PST) Received: from localhost ([::1]:55747 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMR8-0001nP-KK for importer@patchew.org; Thu, 01 Mar 2018 06:31:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMJv-0003jl-Th for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJu-00087k-G2 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:19 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46706) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJu-00086z-7C for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:18 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJt-0000bn-7W for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:39 +0000 Message-Id: <20180301112403.12487-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-11-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 5 +++++ target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/translate-a64.c | 15 ++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index bac9469426..1cf40bda5e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -56,3 +56,8 @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 931a6d3c34..d0b284fec4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -594,3 +594,52 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* + * Floating point comparisons produce an integer result. Softfloat + * routines return float_relation types which we convert to the 0/-1 + * Neon requires. + */ + +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 + +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare_quiet(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f8770ee1e9..fb74dc1c45 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10289,6 +10289,9 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10304,6 +10307,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x17: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10311,6 +10320,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); --=20 2.16.2