From nobody Thu Dec 18 19:36:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519903743095711.5798024809382; Thu, 1 Mar 2018 03:29:03 -0800 (PST) Received: from localhost ([::1]:55730 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMOP-0007h4-01 for importer@patchew.org; Thu, 01 Mar 2018 06:28:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMJu-0003iW-S3 for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJs-00086K-QH for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46704) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJs-00085k-Hy for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:16 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJr-0000b1-Kr for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:15 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:37 +0000 Message-Id: <20180301112403.12487-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-9-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5dd54b7ac4..4828457b5b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10228,6 +10228,78 @@ static void disas_simd_three_reg_same(DisasContext= *s, uint32_t insn) } } =20 +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 = 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | R= d | + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode =3D extract32(insn, 11, 3); + u =3D extract32(insn, 29, 1); + a =3D extract32(insn, 23, 1); + is_q =3D extract32(insn, 30, 1); + rm =3D extract32(insn, 16, 5); + rn =3D extract32(insn, 5, 5); + rd =3D extract32(insn, 0, 5); + + fpopcode =3D opcode | (a << 3) | (u << 4); + datasize =3D is_q ? 128 : 64; + elements =3D datasize / 16; + + fpst =3D get_fpstatus_ptr(true); + + for (pass =3D 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + clear_vec_high(s, is_q, rd); +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11975,6 +12047,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.16.2