From nobody Thu Dec 18 19:34:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519903576813134.91864623176718; Thu, 1 Mar 2018 03:26:16 -0800 (PST) Received: from localhost ([::1]:55715 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMLl-0005BK-KM for importer@patchew.org; Thu, 01 Mar 2018 06:26:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33669) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1erMJr-0003fx-SV for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1erMJq-00084n-0x for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:15 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46700) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1erMJp-00084T-Ko for qemu-devel@nongnu.org; Thu, 01 Mar 2018 06:24:13 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1erMJo-0000Zq-Ng for qemu-devel@nongnu.org; Thu, 01 Mar 2018 11:24:12 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 1 Mar 2018 11:23:33 +0000 Message-Id: <20180301112403.12487-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180301112403.12487-1-peter.maydell@linaro.org> References: <20180301112403.12487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/42] target/arm/cpu.h: add additional float_status flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alex Benn=C3=A9e Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-5-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 32 ++++++++++++++++++++++------ target/arm/helper.c | 26 ++++++++++++++++++----- target/arm/translate-a64.c | 53 +++++++++++++++++++++++++-----------------= ---- 3 files changed, 75 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25f31a4e21..2b9740878b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -538,19 +538,29 @@ typedef struct CPUARMState { /* scratch space when Tn are not sufficient. */ uint32_t scratch[8]; =20 - /* fp_status is the "normal" fp status. standard_fp_status retains - * values corresponding to the ARM "Standard FPSCR Value", ie - * default-NaN, flush-to-zero, round-to-nearest and is used by - * any operations (generally Neon) which the architecture defines - * as controlled by the standard FPSCR value rather than the FPSCR. + /* There are a number of distinct float control structures: + * + * fp_status: is the "normal" fp status. + * fp_status_fp16: used for half-precision calculations + * standard_fp_status : the ARM "Standard FPSCR Value" + * + * Half-precision operations are governed by a separate + * flush-to-zero control bit in FPSCR:FZ16. We pass a separate + * status structure to control this. + * + * The "Standard FPSCR", ie default-NaN, flush-to-zero, + * round-to-nearest and is used by any operations (generally + * Neon) which the architecture defines as controlled by the + * standard FPSCR value rather than the FPSCR. * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the two fp statuses. This relies on the + * OR of the flags in the three fp statuses. This relies on the * only thing which needs to read the exception flags being * an explicit FPSCR read. */ float_status fp_status; + float_status fp_status_f16; float_status standard_fp_status; =20 /* ZCR_EL[1-3] */ @@ -1190,12 +1200,20 @@ static inline void xpsr_write(CPUARMState *env, uin= t32_t val, uint32_t mask) uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); =20 -/* For A64 the FPSCR is split into two logically distinct registers, +/* FPCR, Floating Point Control Register + * FPSR, Floating Poiht Status Register + * + * For A64 the FPSCR is split into two logically distinct registers, * FPCR and FPSR. However since they still use non-overlapping bits * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07f79f00 + +#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ +#define FPCR_DN (1 << 25) /* Default NaN enable bit */ + static inline uint32_t vfp_get_fpsr(CPUARMState *env) { return vfp_get_fpscr(env) & FPSR_MASK; diff --git a/target/arm/helper.c b/target/arm/helper.c index c5bc69b961..f450eb200f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11103,6 +11103,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_stride << 20); i =3D get_float_exception_flags(&env->vfp.fp_status); i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + i |=3D get_float_exception_flags(&env->vfp.fp_status_f16); fpscr |=3D vfp_exceptbits_from_host(i); return fpscr; } @@ -11160,16 +11161,31 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint= 32_t val) break; } set_float_rounding_mode(i, &env->vfp.fp_status); + set_float_rounding_mode(i, &env->vfp.fp_status_f16); } - if (changed & (1 << 24)) { - set_flush_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_status); - set_flush_inputs_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_st= atus); + if (changed & FPCR_FZ16) { + bool ftz_enabled =3D val & FPCR_FZ16; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + } + if (changed & FPCR_FZ) { + bool ftz_enabled =3D val & FPCR_FZ; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); + } + if (changed & FPCR_DN) { + bool dnan_enabled =3D val & FPCR_DN; + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); } - if (changed & (1 << 25)) - set_default_nan_mode((val & (1 << 25)) !=3D 0, &env->vfp.fp_status= ); =20 + /* The exception flags are ORed together when we read fpscr so we + * only need to preserve the current state in one of our + * float_status values. + */ i =3D vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c88539d62..2c64d2b3fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -637,16 +637,21 @@ static void write_fp_sreg(DisasContext *s, int reg, T= CGv_i32 v) tcg_temp_free_i64(tmp); } =20 -static TCGv_ptr get_fpstatus_ptr(void) +static TCGv_ptr get_fpstatus_ptr(bool is_f16) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); int offset; =20 - /* In A64 all instructions (both FP and Neon) use the FPCR; - * there is no equivalent of the A32 Neon "standard FPSCR value" - * and all operations use vfp.fp_status. + /* In A64 all instructions (both FP and Neon) use the FPCR; there + * is no equivalent of the A32 Neon "standard FPSCR value". + * However half-precision operations operate under a different + * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. */ - offset =3D offsetof(CPUARMState, vfp.fp_status); + if (is_f16) { + offset =3D offsetof(CPUARMState, vfp.fp_status_f16); + } else { + offset =3D offsetof(CPUARMState, vfp.fp_status); + } tcg_gen_addi_ptr(statusptr, cpu_env, offset); return statusptr; } @@ -4423,7 +4428,7 @@ static void handle_fp_compare(DisasContext *s, bool i= s_double, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_vn, tcg_vm; @@ -4598,7 +4603,7 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) TCGv_i32 tcg_op; TCGv_i32 tcg_res; =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_sreg(s, rn); tcg_res =3D tcg_temp_new_i32(); =20 @@ -4660,7 +4665,7 @@ static void handle_fp_1src_double(DisasContext *s, in= t opcode, int rd, int rn) return; } =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_dreg(s, rn); tcg_res =3D tcg_temp_new_i64(); =20 @@ -4840,7 +4845,7 @@ static void handle_fp_2src_single(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); =20 @@ -4893,7 +4898,7 @@ static void handle_fp_2src_double(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i64(); - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); =20 @@ -4979,7 +4984,7 @@ static void handle_fp_3src_single(DisasContext *s, bo= ol o0, bool o1, { TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); @@ -5017,7 +5022,7 @@ static void handle_fp_3src_double(DisasContext *s, bo= ol o0, bool o1, { TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); @@ -5158,7 +5163,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift; =20 - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); =20 tcg_shift =3D tcg_const_i32(64 - scale); =20 @@ -5870,7 +5875,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) TCGv_i32 tcg_elt1 =3D tcg_temp_new_i32(); TCGv_i32 tcg_elt2 =3D tcg_temp_new_i32(); TCGv_i32 tcg_elt3 =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 assert(esize =3D=3D 32); assert(elements =3D=3D 4); @@ -6372,7 +6377,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) } =20 size =3D extract32(size, 0, 1) ? 3 : 2; - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); break; default: unallocated_encoding(s); @@ -6864,7 +6869,7 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, int fracbits, int size) { bool is_double =3D size =3D=3D 3 ? true : false; - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); TCGv_i32 tcg_shift =3D tcg_const_i32(fracbits); TCGv_i64 tcg_int =3D tcg_temp_new_i64(); TCGMemOp mop =3D size | (is_signed ? MO_SIGN : 0); @@ -6980,7 +6985,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); tcg_shift =3D tcg_const_i32(fracbits); =20 if (is_double) { @@ -7326,7 +7331,7 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, int fpopcode, int rd, int rn, int rm) { int pass; - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 for (pass =3D 0; pass < elements; pass++) { if (size) { @@ -7790,7 +7795,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, return; } =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -7897,7 +7902,7 @@ static void handle_2misc_reciprocal(DisasContext *s, = int opcode, int size, int rn, int rd) { bool is_double =3D (size =3D=3D 3); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -8296,7 +8301,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_rmode =3D NULL; tcg_fpstatus =3D NULL; @@ -9516,7 +9521,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, =20 /* Floating point operations need fpst */ if (opcode >=3D 0x58) { - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); } else { fpst =3D NULL; } @@ -10676,7 +10681,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } =20 if (need_fpstatus) { - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_fpstatus =3D NULL; } @@ -11056,7 +11061,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 if (is_fp) { - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); } else { fpst =3D NULL; } --=20 2.16.2