From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151985012182416.91123633392749; Wed, 28 Feb 2018 12:35:21 -0800 (PST) Received: from localhost ([::1]:46708 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8RZ-0001p2-5c for importer@patchew.org; Wed, 28 Feb 2018 15:35:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PW-0000Wr-4v for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PS-00020F-UI for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:10 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58462 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PS-0001v2-Nw; Wed, 28 Feb 2018 15:33:06 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8PX-0003Ba-0m; Wed, 28 Feb 2018 20:33:12 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:32 +0000 Message-Id: <20180228203243.1413-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 01/12] macio: embed DBDMA device directly within macio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The current recommendation is to embed subdevices directly within their con= tainer device, so do this for the DBDMA device. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/macio.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 024f8557ab..7174135c8b 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -42,7 +42,7 @@ typedef struct MacIOState =20 MemoryRegion bar; CUDAState cuda; - DBDMAState *dbdma; + DBDMAState dbdma; MemoryRegion *pic_mem; MemoryRegion *escc_mem; uint64_t frequency; @@ -129,12 +129,12 @@ static void macio_common_realize(PCIDevice *d, Error = **errp) SysBusDevice *sysbus_dev; Error *err =3D NULL; =20 - object_property_set_bool(OBJECT(s->dbdma), true, "realized", &err); + object_property_set_bool(OBJECT(&s->dbdma), true, "realized", &err); if (err) { error_propagate(errp, err); return; } - sysbus_dev =3D SYS_BUS_DEVICE(s->dbdma); + sysbus_dev =3D SYS_BUS_DEVICE(&s->dbdma); memory_region_add_subregion(&s->bar, 0x08000, sysbus_mmio_get_region(sysbus_dev, 0)); =20 @@ -161,7 +161,7 @@ static void macio_realize_ide(MacIOState *s, MACIOIDESt= ate *ide, sysbus_connect_irq(sysbus_dev, 0, irq0); sysbus_connect_irq(sysbus_dev, 1, irq1); qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid); - object_property_set_link(OBJECT(ide), OBJECT(s->dbdma), "dbdma", errp); + object_property_set_link(OBJECT(ide), OBJECT(&s->dbdma), "dbdma", errp= ); macio_ide_register_dma(ide); =20 object_property_set_bool(OBJECT(ide), true, "realized", errp); @@ -344,8 +344,9 @@ static void macio_instance_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); =20 - s->dbdma =3D MAC_DBDMA(object_new(TYPE_MAC_DBDMA)); - object_property_add_child(obj, "dbdma", OBJECT(s->dbdma), NULL); + object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA); + qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default()); + object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL); } =20 static const VMStateDescription vmstate_macio_oldworld =3D { --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850464542397.76586142906046; Wed, 28 Feb 2018 12:41:04 -0800 (PST) Received: from localhost ([::1]:46757 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8X9-0007Hq-BE for importer@patchew.org; Wed, 28 Feb 2018 15:41:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PW-0000Wv-64 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PU-00021E-Dv for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:10 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58467 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PU-0001x6-3A; Wed, 28 Feb 2018 15:33:08 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8PY-0003Ba-BT; Wed, 28 Feb 2018 20:33:14 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:33 +0000 Message-Id: <20180228203243.1413-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 02/12] macio: move ESCC device within the macio device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Now that the ESCC device is instantiated directly via qdev, move it to with= in the macio device and wire up the IRQs and memory regions using the sysbus A= PI. This enables to remove the now-obsolete escc_mem parameter to the macio_ini= t() function. (Note this patch also contains small touch-ups to the formatting in macio_escc_legacy_setup() and ppc_heathrow_init() in order to keep checkpat= ch happy) Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/macio.c | 60 ++++++++++++++++++++++++++++++++++++-----------= ---- hw/ppc/mac.h | 3 +-- hw/ppc/mac_newworld.c | 37 ++++++++----------------------- hw/ppc/mac_oldworld.c | 38 +++++++++----------------------- 4 files changed, 63 insertions(+), 75 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 7174135c8b..1c10d8a1d7 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -43,8 +43,8 @@ typedef struct MacIOState MemoryRegion bar; CUDAState cuda; DBDMAState dbdma; + ESCCState escc; MemoryRegion *pic_mem; - MemoryRegion *escc_mem; uint64_t frequency; } MacIOState; =20 @@ -56,7 +56,7 @@ typedef struct OldWorldMacIOState { MacIOState parent_obj; /*< public >*/ =20 - qemu_irq irqs[5]; + qemu_irq irqs[7]; =20 MacIONVRAMState nvram; MACIOIDEState ide[2]; @@ -69,7 +69,7 @@ typedef struct NewWorldMacIOState { /*< private >*/ MacIOState parent_obj; /*< public >*/ - qemu_irq irqs[5]; + qemu_irq irqs[7]; MACIOIDEState ide[2]; } NewWorldMacIOState; =20 @@ -84,10 +84,12 @@ typedef struct NewWorldMacIOState { * * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwor= k/CHRP_IORef_1.0.pdf */ -static void macio_escc_legacy_setup(MacIOState *macio_state) +static void macio_escc_legacy_setup(MacIOState *s) { + ESCCState *escc =3D ESCC(&s->escc); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(escc); MemoryRegion *escc_legacy =3D g_new(MemoryRegion, 1); - MemoryRegion *bar =3D &macio_state->bar; + MemoryRegion *bar =3D &s->bar; int i; static const int maps[] =3D { 0x00, 0x00, /* Command B */ @@ -102,25 +104,26 @@ static void macio_escc_legacy_setup(MacIOState *macio= _state) 0xb0, 0xb0, /* Detect AB */ }; =20 - memory_region_init(escc_legacy, OBJECT(macio_state), "escc-legacy", 25= 6); + memory_region_init(escc_legacy, OBJECT(s), "escc-legacy", 256); for (i =3D 0; i < ARRAY_SIZE(maps); i +=3D 2) { MemoryRegion *port =3D g_new(MemoryRegion, 1); - memory_region_init_alias(port, OBJECT(macio_state), "escc-legacy-p= ort", - macio_state->escc_mem, maps[i+1], 0x2); + memory_region_init_alias(port, OBJECT(s), "escc-legacy-port", + sysbus_mmio_get_region(sbd, 0), + maps[i + 1], 0x2); memory_region_add_subregion(escc_legacy, maps[i], port); } =20 memory_region_add_subregion(bar, 0x12000, escc_legacy); } =20 -static void macio_bar_setup(MacIOState *macio_state) +static void macio_bar_setup(MacIOState *s) { - MemoryRegion *bar =3D &macio_state->bar; + ESCCState *escc =3D ESCC(&s->escc); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(escc); + MemoryRegion *bar =3D &s->bar; =20 - if (macio_state->escc_mem) { - memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem); - macio_escc_legacy_setup(macio_state); - } + memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, = 0)); + macio_escc_legacy_setup(s); } =20 static void macio_common_realize(PCIDevice *d, Error **errp) @@ -147,6 +150,12 @@ static void macio_common_realize(PCIDevice *d, Error *= *errp) memory_region_add_subregion(&s->bar, 0x16000, sysbus_mmio_get_region(sysbus_dev, 0)); =20 + object_property_set_bool(OBJECT(&s->escc), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + macio_bar_setup(s); pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); } @@ -185,6 +194,10 @@ static void macio_oldworld_realize(PCIDevice *d, Error= **errp) sysbus_dev =3D SYS_BUS_DEVICE(&s->cuda); sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); =20 + sysbus_dev =3D SYS_BUS_DEVICE(&s->escc); + sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); + sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]); + object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -297,6 +310,10 @@ static void macio_newworld_realize(PCIDevice *d, Error= **errp) sysbus_dev =3D SYS_BUS_DEVICE(&s->cuda); sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]); =20 + sysbus_dev =3D SYS_BUS_DEVICE(&s->escc); + sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]); + sysbus_connect_irq(sysbus_dev, 1, ns->irqs[cur_irq++]); + if (s->pic_mem) { /* OpenPIC */ memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem); @@ -347,6 +364,17 @@ static void macio_instance_init(Object *obj) object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA); qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default()); object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL); + + object_initialize(&s->escc, sizeof(s->escc), TYPE_ESCC); + qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); + qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); + qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); + qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hds[0]); + qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hds[1]); + qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); + qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); + qdev_set_parent_bus(DEVICE(&s->escc), sysbus_get_default()); + object_property_add_child(obj, "escc", OBJECT(&s->escc), NULL); } =20 static const VMStateDescription vmstate_macio_oldworld =3D { @@ -444,13 +472,11 @@ static void macio_register_types(void) type_init(macio_register_types) =20 void macio_init(PCIDevice *d, - MemoryRegion *pic_mem, - MemoryRegion *escc_mem) + MemoryRegion *pic_mem) { MacIOState *macio_state =3D MACIO(d); =20 macio_state->pic_mem =3D pic_mem; - macio_state->escc_mem =3D escc_mem; /* Note: this code is strongly inspirated from the corresponding code in PearPC */ qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency", diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 4702194f3f..261b519aa5 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -76,8 +76,7 @@ void macio_ide_init_drives(MACIOIDEState *ide, DriveInfo = **hd_table); void macio_ide_register_dma(MACIOIDEState *ide); =20 void macio_init(PCIDevice *dev, - MemoryRegion *pic_mem, - MemoryRegion *escc_mem); + MemoryRegion *pic_mem); =20 /* Heathrow PIC */ qemu_irq *heathrow_pic_init(MemoryRegion **pmem, diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 4e1298ee50..5e82158759 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -159,8 +159,7 @@ static void ppc_core99_init(MachineState *machine) MacIONVRAMState *nvr; int bios_size, ndrv_size; uint8_t *ndrv_file; - MemoryRegion *pic_mem, *escc_mem; - MemoryRegion *escc_bar =3D g_new(MemoryRegion, 1); + MemoryRegion *pic_mem; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; @@ -368,36 +367,18 @@ static void ppc_core99_init(MachineState *machine) tbfreq =3D TBFREQ; } =20 - /* init basic PC hardware */ - - dev =3D qdev_create(NULL, TYPE_ESCC); - qdev_prop_set_uint32(dev, "disabled", 0); - qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); - qdev_prop_set_uint32(dev, "it_shift", 4); - qdev_prop_set_chr(dev, "chrA", serial_hds[0]); - qdev_prop_set_chr(dev, "chrB", serial_hds[1]); - qdev_prop_set_uint32(dev, "chnAtype", escc_serial); - qdev_prop_set_uint32(dev, "chnBtype", escc_serial); - qdev_init_nofail(dev); - - s =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, pic[0x24]); - sysbus_connect_irq(s, 1, pic[0x25]); - - escc_mem =3D &ESCC(s)->mmio; - - memory_region_init_alias(escc_bar, NULL, "escc-bar", - escc_mem, 0, memory_region_size(escc_mem)); - + /* MacIO */ macio =3D pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); dev =3D DEVICE(macio); qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ - qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ - qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ - qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ - qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ + qdev_connect_gpio_out(dev, 1, pic[0x24]); /* ESCC-B */ + qdev_connect_gpio_out(dev, 2, pic[0x25]); /* ESCC-A */ + qdev_connect_gpio_out(dev, 3, pic[0x0d]); /* IDE */ + qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE DMA */ + qdev_connect_gpio_out(dev, 5, pic[0x0e]); /* IDE */ + qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE DMA */ qdev_prop_set_uint64(dev, "frequency", tbfreq); - macio_init(macio, pic_mem, escc_bar); + macio_init(macio, pic_mem); =20 /* We only emulate 2 out of 3 IDE controllers for now */ ide_drive_get(hd, ARRAY_SIZE(hd)); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index d0d21d2392..4401ce5af2 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -99,12 +99,10 @@ static void ppc_heathrow_init(MachineState *machine) int bios_size, ndrv_size; uint8_t *ndrv_file; MemoryRegion *pic_mem; - MemoryRegion *escc_mem, *escc_bar =3D g_new(MemoryRegion, 1); uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; uint64_t tbfreq; - SysBusDevice *s; =20 linux_boot =3D (kernel_filename !=3D NULL); =20 @@ -265,40 +263,24 @@ static void ppc_heathrow_init(MachineState *machine) get_system_io()); pci_vga_init(pci_bus); =20 - dev =3D qdev_create(NULL, TYPE_ESCC); - qdev_prop_set_uint32(dev, "disabled", 0); - qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); - qdev_prop_set_uint32(dev, "it_shift", 4); - qdev_prop_set_chr(dev, "chrA", serial_hds[0]); - qdev_prop_set_chr(dev, "chrB", serial_hds[1]); - qdev_prop_set_uint32(dev, "chnBtype", escc_serial); - qdev_prop_set_uint32(dev, "chnAtype", escc_serial); - qdev_init_nofail(dev); - - s =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, pic[0x10]); - sysbus_connect_irq(s, 1, pic[0x0f]); - - escc_mem =3D &ESCC(s)->mmio; - - memory_region_init_alias(escc_bar, NULL, "escc-bar", - escc_mem, 0, memory_region_size(escc_mem)); - - for(i =3D 0; i < nb_nics; i++) + for (i =3D 0; i < nb_nics; i++) { pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); - + } =20 ide_drive_get(hd, ARRAY_SIZE(hd)); =20 + /* MacIO */ macio =3D pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); dev =3D DEVICE(macio); qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ - qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ - qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ - qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ - qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ + qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */ + qdev_connect_gpio_out(dev, 2, pic[0x0F]); /* ESCC-A */ + qdev_connect_gpio_out(dev, 3, pic[0x0D]); /* IDE-0 */ + qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE-0 DMA */ + qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */ + qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */ qdev_prop_set_uint64(dev, "frequency", tbfreq); - macio_init(macio, pic_mem, escc_bar); + macio_init(macio, pic_mem); =20 macio_ide =3D MACIO_IDE(object_resolve_path_component(OBJECT(macio), "ide[0]")); --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850306193527.5536811677583; Wed, 28 Feb 2018 12:38:26 -0800 (PST) Received: from localhost ([::1]:46731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Ua-0004e1-UI for importer@patchew.org; Wed, 28 Feb 2018 15:38:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59194) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Pa-0000Zq-IC for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PX-000251-97 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:14 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58469 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PW-0001yB-S6; Wed, 28 Feb 2018 15:33:11 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pa-0003Ba-MU; Wed, 28 Feb 2018 20:33:16 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:34 +0000 Message-Id: <20180228203243.1413-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 03/12] heathrow: QOMify heathrow PIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland --- hw/intc/heathrow_pic.c | 126 +++++++++++++++++++++++--------------= ---- include/hw/intc/heathrow_pic.h | 49 ++++++++++++++++ 2 files changed, 119 insertions(+), 56 deletions(-) create mode 100644 include/hw/intc/heathrow_pic.h diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c index 171f5ed814..7bf44e0d86 100644 --- a/hw/intc/heathrow_pic.c +++ b/hw/intc/heathrow_pic.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/ppc/mac.h" +#include "hw/intc/heathrow_pic.h" =20 /* debug PIC */ //#define DEBUG_PIC @@ -36,39 +37,27 @@ #define PIC_DPRINTF(fmt, ...) #endif =20 -typedef struct HeathrowPIC { - uint32_t events; - uint32_t mask; - uint32_t levels; - uint32_t level_triggered; -} HeathrowPIC; - -typedef struct HeathrowPICS { - MemoryRegion mem; - HeathrowPIC pics[2]; - qemu_irq *irqs; -} HeathrowPICS; - -static inline int check_irq(HeathrowPIC *pic) +static inline int heathrow_check_irq(HeathrowPICState *pic) { return (pic->events | (pic->levels & pic->level_triggered)) & pic->mas= k; } =20 /* update the CPU irq state */ -static void heathrow_pic_update(HeathrowPICS *s) +static void heathrow_update_irq(HeathrowState *s) { - if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) { + if (heathrow_check_irq(&s->pics[0]) || + heathrow_check_irq(&s->pics[1])) { qemu_irq_raise(s->irqs[0]); } else { qemu_irq_lower(s->irqs[0]); } } =20 -static void pic_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static void heathrow_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) { - HeathrowPICS *s =3D opaque; - HeathrowPIC *pic; + HeathrowState *s =3D opaque; + HeathrowPICState *pic; unsigned int n; =20 n =3D ((addr & 0xfff) - 0x10) >> 4; @@ -79,24 +68,24 @@ static void pic_write(void *opaque, hwaddr addr, switch(addr & 0xf) { case 0x04: pic->mask =3D value; - heathrow_pic_update(s); + heathrow_update_irq(s); break; case 0x08: /* do not reset level triggered IRQs */ value &=3D ~pic->level_triggered; pic->events &=3D ~value; - heathrow_pic_update(s); + heathrow_update_irq(s); break; default: break; } } =20 -static uint64_t pic_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t heathrow_read(void *opaque, hwaddr addr, + unsigned size) { - HeathrowPICS *s =3D opaque; - HeathrowPIC *pic; + HeathrowState *s =3D opaque; + HeathrowPICState *pic; unsigned int n; uint32_t value; =20 @@ -124,16 +113,16 @@ static uint64_t pic_read(void *opaque, hwaddr addr, return value; } =20 -static const MemoryRegionOps heathrow_pic_ops =3D { - .read =3D pic_read, - .write =3D pic_write, +static const MemoryRegionOps heathrow_ops =3D { + .read =3D heathrow_read, + .write =3D heathrow_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 -static void heathrow_pic_set_irq(void *opaque, int num, int level) +static void heathrow_set_irq(void *opaque, int num, int level) { - HeathrowPICS *s =3D opaque; - HeathrowPIC *pic; + HeathrowState *s =3D opaque; + HeathrowPICState *pic; unsigned int irq_bit; =20 #if defined(DEBUG) @@ -153,7 +142,7 @@ static void heathrow_pic_set_irq(void *opaque, int num,= int level) } else { pic->levels &=3D ~irq_bit; } - heathrow_pic_update(s); + heathrow_update_irq(s); } =20 static const VMStateDescription vmstate_heathrow_pic_one =3D { @@ -161,54 +150,79 @@ static const VMStateDescription vmstate_heathrow_pic_= one =3D { .version_id =3D 0, .minimum_version_id =3D 0, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(events, HeathrowPIC), - VMSTATE_UINT32(mask, HeathrowPIC), - VMSTATE_UINT32(levels, HeathrowPIC), - VMSTATE_UINT32(level_triggered, HeathrowPIC), + VMSTATE_UINT32(events, HeathrowPICState), + VMSTATE_UINT32(mask, HeathrowPICState), + VMSTATE_UINT32(levels, HeathrowPICState), + VMSTATE_UINT32(level_triggered, HeathrowPICState), VMSTATE_END_OF_LIST() } }; =20 -static const VMStateDescription vmstate_heathrow_pic =3D { +static const VMStateDescription vmstate_heathrow =3D { .name =3D "heathrow_pic", .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_STRUCT_ARRAY(pics, HeathrowPICS, 2, 1, - vmstate_heathrow_pic_one, HeathrowPIC), + VMSTATE_STRUCT_ARRAY(pics, HeathrowState, 2, 1, + vmstate_heathrow_pic_one, HeathrowPICState), VMSTATE_END_OF_LIST() } }; =20 -static void heathrow_pic_reset_one(HeathrowPIC *s) +static void heathrow_reset(DeviceState *d) { - memset(s, '\0', sizeof(HeathrowPIC)); + HeathrowState *s =3D HEATHROW(d); + + s->pics[0].level_triggered =3D 0; + s->pics[1].level_triggered =3D 0x1ff00000; } =20 -static void heathrow_pic_reset(void *opaque) +static void heathrow_init(Object *obj) { - HeathrowPICS *s =3D opaque; - - heathrow_pic_reset_one(&s->pics[0]); - heathrow_pic_reset_one(&s->pics[1]); + HeathrowState *s =3D HEATHROW(obj); =20 - s->pics[0].level_triggered =3D 0; - s->pics[1].level_triggered =3D 0x1ff00000; + memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s, + "heathrow-pic", 0x1000); } =20 qemu_irq *heathrow_pic_init(MemoryRegion **pmem, int nb_cpus, qemu_irq **irqs) { - HeathrowPICS *s; + DeviceState *d; + HeathrowState *s; =20 - s =3D g_malloc0(sizeof(HeathrowPICS)); + d =3D qdev_create(NULL, TYPE_HEATHROW); + qdev_init_nofail(d); + + s =3D HEATHROW(d); /* only 1 CPU */ s->irqs =3D irqs[0]; - memory_region_init_io(&s->mem, NULL, &heathrow_pic_ops, s, - "heathrow-pic", 0x1000); + *pmem =3D &s->mem; =20 - vmstate_register(NULL, -1, &vmstate_heathrow_pic, s); - qemu_register_reset(heathrow_pic_reset, s); - return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64); + return qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS); +} + +static void heathrow_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->reset =3D heathrow_reset; + dc->vmsd =3D &vmstate_heathrow; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } + +static const TypeInfo heathrow_type_info =3D { + .name =3D TYPE_HEATHROW, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HeathrowState), + .instance_init =3D heathrow_init, + .class_init =3D heathrow_class_init, +}; + +static void heathrow_register_types(void) +{ + type_register_static(&heathrow_type_info); +} + +type_init(heathrow_register_types) diff --git a/include/hw/intc/heathrow_pic.h b/include/hw/intc/heathrow_pic.h new file mode 100644 index 0000000000..bc3ffaab87 --- /dev/null +++ b/include/hw/intc/heathrow_pic.h @@ -0,0 +1,49 @@ +/* + * Heathrow PIC support (OldWorld PowerMac) + * + * Copyright (c) 2005-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HEATHROW_H +#define HEATHROW_H + +#define TYPE_HEATHROW "heathrow" +#define HEATHROW(obj) OBJECT_CHECK(HeathrowState, (obj), TYPE_HEATHROW) + +typedef struct HeathrowPICState { + uint32_t events; + uint32_t mask; + uint32_t levels; + uint32_t level_triggered; +} HeathrowPICState; + +typedef struct HeathrowState { + SysBusDevice parent_obj; + + MemoryRegion mem; + HeathrowPICState pics[2]; + qemu_irq *irqs; +} HeathrowState; + +#define HEATHROW_NUM_IRQS 64 + +#endif /* HEATHROW_H */ --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850307105954.1567470482165; Wed, 28 Feb 2018 12:38:27 -0800 (PST) Received: from localhost ([::1]:46732 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Ub-0004fR-QX for importer@patchew.org; Wed, 28 Feb 2018 15:38:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PZ-0000ZK-S2 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PX-00024U-2Q for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:13 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58472 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PW-0001yq-N0; Wed, 28 Feb 2018 15:33:10 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pc-0003Ba-PQ; Wed, 28 Feb 2018 20:33:17 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:35 +0000 Message-Id: <20180228203243.1413-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 04/12] heathrow: convert to trace-events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland --- hw/intc/heathrow_pic.c | 32 +++++++++++--------------------- hw/intc/trace-events | 5 +++++ 2 files changed, 16 insertions(+), 21 deletions(-) diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c index 7bf44e0d86..5fd2b33a12 100644 --- a/hw/intc/heathrow_pic.c +++ b/hw/intc/heathrow_pic.c @@ -26,16 +26,7 @@ #include "hw/hw.h" #include "hw/ppc/mac.h" #include "hw/intc/heathrow_pic.h" - -/* debug PIC */ -//#define DEBUG_PIC - -#ifdef DEBUG_PIC -#define PIC_DPRINTF(fmt, ...) \ - do { printf("PIC: " fmt , ## __VA_ARGS__); } while (0) -#else -#define PIC_DPRINTF(fmt, ...) -#endif +#include "trace.h" =20 static inline int heathrow_check_irq(HeathrowPICState *pic) { @@ -61,7 +52,7 @@ static void heathrow_write(void *opaque, hwaddr addr, unsigned int n; =20 n =3D ((addr & 0xfff) - 0x10) >> 4; - PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value); + trace_heathrow_write(addr, n, value); if (n >=3D 2) return; pic =3D &s->pics[n]; @@ -109,7 +100,7 @@ static uint64_t heathrow_read(void *opaque, hwaddr addr, break; } } - PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value); + trace_heathrow_read(addr, n, value); return value; } =20 @@ -124,24 +115,23 @@ static void heathrow_set_irq(void *opaque, int num, i= nt level) HeathrowState *s =3D opaque; HeathrowPICState *pic; unsigned int irq_bit; + int last_level; =20 -#if defined(DEBUG) - { - static int last_level[64]; - if (last_level[num] !=3D level) { - PIC_DPRINTF("set_irq: num=3D0x%02x level=3D%d\n", num, level); - last_level[num] =3D level; - } - } -#endif pic =3D &s->pics[1 - (num >> 5)]; irq_bit =3D 1 << (num & 0x1f); + last_level =3D (pic->levels & irq_bit) ? 1 : 0; + if (level) { pic->events |=3D irq_bit & ~pic->level_triggered; pic->levels |=3D irq_bit; } else { pic->levels &=3D ~irq_bit; } + + if (last_level !=3D level) { + trace_heathrow_set_irq(num, level); + } + heathrow_update_irq(s); } =20 diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 4092d2825e..55e8c2570c 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -186,3 +186,8 @@ nvic_complete_irq(int irq, bool secure) "NVIC complete = IRQ %d (secure %d)" nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to = %d" nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysre= g read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysr= eg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" + +# hw/intc/heathrow_pic.c +heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 +heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 +heathrow_set_irq(int num, int level) "set_irq: num=3D0x%02x level=3D%d" --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850146038812.4807054782277; Wed, 28 Feb 2018 12:35:46 -0800 (PST) Received: from localhost ([::1]:46712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8S0-0002CT-NO for importer@patchew.org; Wed, 28 Feb 2018 15:35:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PW-0000Wq-4t for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PS-00020O-Vt for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:10 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58476 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PS-0001zm-O9; Wed, 28 Feb 2018 15:33:06 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pe-0003Ba-5z; Wed, 28 Feb 2018 20:33:19 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:36 +0000 Message-Id: <20180228203243.1413-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 05/12] heathrow: change heathrow_pic_init() to return the heathrow device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This enables the device to be made available during the setup of the Old Wo= rld machine. In order to pass back the previous set of IRQs we temporarily intr= oduce a new pic_irqs parameter until it can be removed. An additional benefit of this change is that it is also possible to remove = the pic_mem pointer used for macio by accessing the memory region via sysbus. Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson --- hw/intc/heathrow_pic.c | 10 ++++++---- hw/ppc/mac.h | 4 ++-- hw/ppc/mac_oldworld.c | 9 +++++---- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c index 5fd2b33a12..393fdd7326 100644 --- a/hw/intc/heathrow_pic.c +++ b/hw/intc/heathrow_pic.c @@ -170,13 +170,15 @@ static void heathrow_reset(DeviceState *d) static void heathrow_init(Object *obj) { HeathrowState *s =3D HEATHROW(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s, "heathrow-pic", 0x1000); + sysbus_init_mmio(sbd, &s->mem); } =20 -qemu_irq *heathrow_pic_init(MemoryRegion **pmem, - int nb_cpus, qemu_irq **irqs) +DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs, + qemu_irq **pic_irqs) { DeviceState *d; HeathrowState *s; @@ -188,9 +190,9 @@ qemu_irq *heathrow_pic_init(MemoryRegion **pmem, /* only 1 CPU */ s->irqs =3D irqs[0]; =20 - *pmem =3D &s->mem; + *pic_irqs =3D qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQ= S); =20 - return qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS); + return d; } =20 static void heathrow_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 261b519aa5..5b5fffdff3 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -79,8 +79,8 @@ void macio_init(PCIDevice *dev, MemoryRegion *pic_mem); =20 /* Heathrow PIC */ -qemu_irq *heathrow_pic_init(MemoryRegion **pmem, - int nb_cpus, qemu_irq **irqs); +DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs, + qemu_irq **pic_irqs); =20 /* Grackle PCI */ #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost" diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 4401ce5af2..06a61220cb 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -94,11 +94,11 @@ static void ppc_heathrow_init(MachineState *machine) PCIBus *pci_bus; PCIDevice *macio; MACIOIDEState *macio_ide; - DeviceState *dev; + DeviceState *dev, *pic_dev; + SysBusDevice *sbd; BusState *adb_bus; int bios_size, ndrv_size; uint8_t *ndrv_file; - MemoryRegion *pic_mem; uint16_t ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; @@ -257,7 +257,7 @@ static void ppc_heathrow_init(MachineState *machine) error_report("Only 6xx bus is supported on heathrow machine"); exit(1); } - pic =3D heathrow_pic_init(&pic_mem, 1, heathrow_irqs); + pic_dev =3D heathrow_pic_init(1, heathrow_irqs, &pic); pci_bus =3D pci_grackle_init(0xfec00000, pic, get_system_memory(), get_system_io()); @@ -280,7 +280,8 @@ static void ppc_heathrow_init(MachineState *machine) qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */ qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */ qdev_prop_set_uint64(dev, "frequency", tbfreq); - macio_init(macio, pic_mem); + sbd =3D SYS_BUS_DEVICE(pic_dev); + macio_init(macio, sysbus_mmio_get_region(sbd, 0)); =20 macio_ide =3D MACIO_IDE(object_resolve_path_component(OBJECT(macio), "ide[0]")); --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850309929629.6408582810666; Wed, 28 Feb 2018 12:38:29 -0800 (PST) Received: from localhost ([::1]:46733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Ue-0004ho-GP for importer@patchew.org; Wed, 28 Feb 2018 15:38:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59017) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PW-0000X2-EQ for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PU-00021o-Ue for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:10 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58479 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PU-000218-NX; Wed, 28 Feb 2018 15:33:08 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pf-0003Ba-Lq; Wed, 28 Feb 2018 20:33:21 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:37 +0000 Message-Id: <20180228203243.1413-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 06/12] macio: move macio related structures and defines into separate macio.h file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/macio/macio.c | 43 +------------------------ hw/ppc/mac.h | 3 -- hw/ppc/mac_newworld.c | 1 + hw/ppc/mac_oldworld.c | 1 + include/hw/misc/macio/macio.h | 75 +++++++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 78 insertions(+), 45 deletions(-) create mode 100644 include/hw/misc/macio/macio.h diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 1c10d8a1d7..4e502ede2e 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -30,48 +30,7 @@ #include "hw/pci/pci.h" #include "hw/ppc/mac_dbdma.h" #include "hw/char/escc.h" - -#define TYPE_MACIO "macio" -#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO) - -typedef struct MacIOState -{ - /*< private >*/ - PCIDevice parent; - /*< public >*/ - - MemoryRegion bar; - CUDAState cuda; - DBDMAState dbdma; - ESCCState escc; - MemoryRegion *pic_mem; - uint64_t frequency; -} MacIOState; - -#define OLDWORLD_MACIO(obj) \ - OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO) - -typedef struct OldWorldMacIOState { - /*< private >*/ - MacIOState parent_obj; - /*< public >*/ - - qemu_irq irqs[7]; - - MacIONVRAMState nvram; - MACIOIDEState ide[2]; -} OldWorldMacIOState; - -#define NEWWORLD_MACIO(obj) \ - OBJECT_CHECK(NewWorldMacIOState, (obj), TYPE_NEWWORLD_MACIO) - -typedef struct NewWorldMacIOState { - /*< private >*/ - MacIOState parent_obj; - /*< public >*/ - qemu_irq irqs[7]; - MACIOIDEState ide[2]; -} NewWorldMacIOState; +#include "hw/misc/macio/macio.h" =20 /* * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 5b5fffdff3..a02f797598 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -47,9 +47,6 @@ =20 =20 /* MacIO */ -#define TYPE_OLDWORLD_MACIO "macio-oldworld" -#define TYPE_NEWWORLD_MACIO "macio-newworld" - #define TYPE_MACIO_IDE "macio-ide" #define MACIO_IDE(obj) OBJECT_CHECK(MACIOIDEState, (obj), TYPE_MACIO_IDE) =20 diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 5e82158759..396216954e 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -60,6 +60,7 @@ #include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" +#include "hw/misc/macio/macio.h" #include "hw/ppc/openpic.h" #include "hw/ide.h" #include "hw/loader.h" diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 06a61220cb..5903ff47d3 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -37,6 +37,7 @@ #include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" +#include "hw/misc/macio/macio.h" #include "hw/ide.h" #include "hw/loader.h" #include "elf.h" diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h new file mode 100644 index 0000000000..e1e249f898 --- /dev/null +++ b/include/hw/misc/macio/macio.h @@ -0,0 +1,75 @@ +/* + * PowerMac MacIO device emulation + * + * Copyright (c) 2005-2007 Fabrice Bellard + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef MACIO_H +#define MACIO_H + +#include "hw/misc/macio/cuda.h" +#include "hw/ppc/mac_dbdma.h" + +#define TYPE_MACIO "macio" +#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO) + +typedef struct MacIOState { + /*< private >*/ + PCIDevice parent; + /*< public >*/ + + MemoryRegion bar; + CUDAState cuda; + DBDMAState dbdma; + ESCCState escc; + MemoryRegion *pic_mem; + uint64_t frequency; +} MacIOState; + +#define TYPE_OLDWORLD_MACIO "macio-oldworld" +#define OLDWORLD_MACIO(obj) \ + OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO) + +typedef struct OldWorldMacIOState { + /*< private >*/ + MacIOState parent_obj; + /*< public >*/ + + qemu_irq irqs[7]; + + MacIONVRAMState nvram; + MACIOIDEState ide[2]; +} OldWorldMacIOState; + +#define TYPE_NEWWORLD_MACIO "macio-newworld" +#define NEWWORLD_MACIO(obj) \ + OBJECT_CHECK(NewWorldMacIOState, (obj), TYPE_NEWWORLD_MACIO) + +typedef struct NewWorldMacIOState { + /*< private >*/ + MacIOState parent_obj; + /*< public >*/ + qemu_irq irqs[7]; + MACIOIDEState ide[2]; +} NewWorldMacIOState; + +#endif /* MACIO_H */ --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850194258948.8142751139992; Wed, 28 Feb 2018 12:36:34 -0800 (PST) Received: from localhost ([::1]:46717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Sh-0002sL-JP for importer@patchew.org; Wed, 28 Feb 2018 15:36:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8PY-0000YF-8K for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PW-000236-CJ for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:12 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58481 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PW-00022K-5h; Wed, 28 Feb 2018 15:33:10 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Ph-0003Ba-KQ; Wed, 28 Feb 2018 20:33:22 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:38 +0000 Message-Id: <20180228203243.1413-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 07/12] mac_oldworld: use object link to pass heathrow PIC object to macio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also switch macio_oldworld_realize() over to use it rather than using the p= ic_mem memory region directly. Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson --- hw/misc/macio/macio.c | 14 ++++++++++---- hw/ppc/mac_oldworld.c | 8 +++++--- include/hw/misc/macio/macio.h | 2 ++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 4e502ede2e..d4c1d190c4 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -31,6 +31,7 @@ #include "hw/ppc/mac_dbdma.h" #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" +#include "hw/intc/heathrow_pic.h" =20 /* * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", @@ -167,10 +168,10 @@ static void macio_oldworld_realize(PCIDevice *d, Erro= r **errp) sysbus_mmio_get_region(sysbus_dev, 0)); pmac_format_nvram_partition(&os->nvram, os->nvram.size); =20 - if (s->pic_mem) { - /* Heathrow PIC */ - memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem); - } + /* Heathrow PIC */ + sysbus_dev =3D SYS_BUS_DEVICE(os->pic); + memory_region_add_subregion(&s->bar, 0x0, + sysbus_mmio_get_region(sysbus_dev, 0)); =20 /* IDE buses */ for (i =3D 0; i < ARRAY_SIZE(os->ide); i++) { @@ -208,6 +209,11 @@ static void macio_oldworld_init(Object *obj) =20 qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs)); =20 + object_property_add_link(obj, "pic", TYPE_HEATHROW, + (Object **) &os->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM); dev =3D DEVICE(&os->nvram); qdev_prop_set_uint32(dev, "size", 0x2000); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 5903ff47d3..3ac5b19073 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -93,7 +93,7 @@ static void ppc_heathrow_init(MachineState *machine) uint32_t kernel_base, initrd_base, cmdline_base =3D 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; - PCIDevice *macio; + OldWorldMacIOState *macio; MACIOIDEState *macio_ide; DeviceState *dev, *pic_dev; SysBusDevice *sbd; @@ -271,7 +271,7 @@ static void ppc_heathrow_init(MachineState *machine) ide_drive_get(hd, ARRAY_SIZE(hd)); =20 /* MacIO */ - macio =3D pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); + macio =3D OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); dev =3D DEVICE(macio); qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */ @@ -281,8 +281,10 @@ static void ppc_heathrow_init(MachineState *machine) qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */ qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */ qdev_prop_set_uint64(dev, "frequency", tbfreq); + object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", + &error_abort); sbd =3D SYS_BUS_DEVICE(pic_dev); - macio_init(macio, sysbus_mmio_get_region(sbd, 0)); + macio_init(PCI_DEVICE(macio), sysbus_mmio_get_region(sbd, 0)); =20 macio_ide =3D MACIO_IDE(object_resolve_path_component(OBJECT(macio), "ide[0]")); diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h index e1e249f898..843c114c07 100644 --- a/include/hw/misc/macio/macio.h +++ b/include/hw/misc/macio/macio.h @@ -26,6 +26,7 @@ #ifndef MACIO_H #define MACIO_H =20 +#include "hw/intc/heathrow_pic.h" #include "hw/misc/macio/cuda.h" #include "hw/ppc/mac_dbdma.h" =20 @@ -54,6 +55,7 @@ typedef struct OldWorldMacIOState { MacIOState parent_obj; /*< public >*/ =20 + HeathrowState *pic; qemu_irq irqs[7]; =20 MacIONVRAMState nvram; --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850469347568.9868332053235; Wed, 28 Feb 2018 12:41:09 -0800 (PST) Received: from localhost ([::1]:46756 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8X7-0007GF-UP for importer@patchew.org; Wed, 28 Feb 2018 15:41:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Pa-0000a4-Oq for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8PX-000261-T6 for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:14 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58485 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8PX-000244-Jm; Wed, 28 Feb 2018 15:33:11 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pj-0003Ba-4I; Wed, 28 Feb 2018 20:33:24 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:39 +0000 Message-Id: <20180228203243.1413-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 08/12] openpic: move KVM-specific declarations into separate openpic_kvm.h file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is needed before the next patch because the target-dependent kvm stub uses the existing kvm_openpic_connect_vcpu() declaration, making it impossi= ble to move the device-specific declarations into the same file without breaking ppc-linux-user compilation. Signed-off-by: Mark Cave-Ayland --- hw/intc/openpic_kvm.c | 1 + hw/ppc/e500.c | 1 + include/hw/ppc/openpic.h | 3 --- include/hw/ppc/openpic_kvm.h | 7 +++++++ target/ppc/kvm-stub.c | 2 +- 5 files changed, 10 insertions(+), 4 deletions(-) create mode 100644 include/hw/ppc/openpic_kvm.h diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index fa83420254..f1a59e5a85 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -30,6 +30,7 @@ #include "exec/address-spaces.h" #include "hw/hw.h" #include "hw/ppc/openpic.h" +#include "hw/ppc/openpic_kvm.h" #include "hw/pci/msi.h" #include "hw/sysbus.h" #include "sysemu/kvm.h" diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index a40d3ec3e3..13a34f50b7 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -29,6 +29,7 @@ #include "kvm_ppc.h" #include "sysemu/device_tree.h" #include "hw/ppc/openpic.h" +#include "hw/ppc/openpic_kvm.h" #include "hw/ppc/ppc.h" #include "hw/loader.h" #include "elf.h" diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h index e55ce546aa..693e981965 100644 --- a/include/hw/ppc/openpic.h +++ b/include/hw/ppc/openpic.h @@ -28,7 +28,4 @@ enum { #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \ OPENPIC_MAX_TMR) =20 -#define TYPE_KVM_OPENPIC "kvm-openpic" -int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs); - #endif /* OPENPIC_H */ diff --git a/include/hw/ppc/openpic_kvm.h b/include/hw/ppc/openpic_kvm.h new file mode 100644 index 0000000000..9ef4215257 --- /dev/null +++ b/include/hw/ppc/openpic_kvm.h @@ -0,0 +1,7 @@ +#ifndef OPENPIC_KVM_H +#define OPENPIC_KVM_H + +#define TYPE_KVM_OPENPIC "kvm-openpic" +int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs); + +#endif /* OPENPIC_KVM_H */ diff --git a/target/ppc/kvm-stub.c b/target/ppc/kvm-stub.c index efeafca1df..b8aa97f2d4 100644 --- a/target/ppc/kvm-stub.c +++ b/target/ppc/kvm-stub.c @@ -12,7 +12,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" -#include "hw/ppc/openpic.h" +#include "hw/ppc/openpic_kvm.h" =20 int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) { --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850618547945.5687400449458; Wed, 28 Feb 2018 12:43:38 -0800 (PST) Received: from localhost ([::1]:46775 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Zd-0001Ib-Cm for importer@patchew.org; Wed, 28 Feb 2018 15:43:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59272) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Pd-0000bO-1y for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8Pa-000293-Fi for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:33:17 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58488 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8Pa-00027x-0k; Wed, 28 Feb 2018 15:33:14 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pk-0003Ba-Fm; Wed, 28 Feb 2018 20:33:26 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:40 +0000 Message-Id: <20180228203243.1413-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 09/12] openpic: move OpenPIC state and related definitions to openpic.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is to faciliate access to OpenPICState when wiring up the PIC to the m= acio controller. Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson --- hw/intc/openpic.c | 157 -------------------------------------------= --- include/hw/ppc/openpic.h | 159 +++++++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 158 insertions(+), 158 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 9159a06f07..811cee9b26 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -63,10 +63,6 @@ static int get_current_cpu(void); } \ } while (0) =20 -#define MAX_CPU 32 -#define MAX_MSI 8 -#define VID 0x03 /* MPIC version ID */ - /* OpenPIC capability flags */ #define OPENPIC_FLAG_IDR_CRIT (1 << 0) #define OPENPIC_FLAG_ILR (2 << 0) @@ -85,35 +81,6 @@ static int get_current_cpu(void); #define OPENPIC_CPU_REG_START 0x20000 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) =20 -/* Raven */ -#define RAVEN_MAX_CPU 2 -#define RAVEN_MAX_EXT 48 -#define RAVEN_MAX_IRQ 64 -#define RAVEN_MAX_TMR OPENPIC_MAX_TMR -#define RAVEN_MAX_IPI OPENPIC_MAX_IPI - -/* KeyLargo */ -#define KEYLARGO_MAX_CPU 4 -#define KEYLARGO_MAX_EXT 64 -#define KEYLARGO_MAX_IPI 4 -#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) -#define KEYLARGO_MAX_TMR 0 -#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ -/* Timers don't exist but this makes the code happy... */ -#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) - -/* Interrupt definitions */ -#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ -#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ -#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ -#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ = */ -/* First doorbell IRQ */ -#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) - -typedef struct FslMpicInfo { - int max_ext; -} FslMpicInfo; - static FslMpicInfo fsl_mpic_20 =3D { .max_ext =3D 12, }; @@ -211,55 +178,6 @@ static void openpic_cpu_write_internal(void *opaque, h= waddr addr, uint32_t val, int idx); static void openpic_reset(DeviceState *d); =20 -typedef enum IRQType { - IRQ_TYPE_NORMAL =3D 0, - IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ - IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity = */ -} IRQType; - -/* Round up to the nearest 64 IRQs so that the queue length - * won't change when moving between 32 and 64 bit hosts. - */ -#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) - -typedef struct IRQQueue { - unsigned long *queue; - int32_t queue_size; /* Only used for VMSTATE_BITMAP */ - int next; - int priority; -} IRQQueue; - -typedef struct IRQSource { - uint32_t ivpr; /* IRQ vector/priority register */ - uint32_t idr; /* IRQ destination register */ - uint32_t destmask; /* bitmap of CPU destinations */ - int last_cpu; - int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ - int pending; /* TRUE if IRQ is pending */ - IRQType type; - bool level:1; /* level-triggered */ - bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ -} IRQSource; - -#define IVPR_MASK_SHIFT 31 -#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) -#define IVPR_ACTIVITY_SHIFT 30 -#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) -#define IVPR_MODE_SHIFT 29 -#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) -#define IVPR_POLARITY_SHIFT 23 -#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) -#define IVPR_SENSE_SHIFT 22 -#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) - -#define IVPR_PRIORITY_MASK (0xFU << 16) -#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> = 16)) -#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) - -/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ -#define IDR_EP 0x80000000 /* external pin */ -#define IDR_CI 0x40000000 /* critical interrupt */ - /* Convert between openpic clock ticks and nanosecs. In the hardware the = clock frequency is driven by board inputs to the PIC which the PIC would then divide by 4 or 8. For now hard code to 25MZ. @@ -275,81 +193,6 @@ static inline uint64_t ticks_to_ns(uint64_t ticks) return ticks * OPENPIC_TIMER_NS_PER_TICK; } =20 -typedef struct OpenPICTimer { - uint32_t tccr; /* Global timer current count register */ - uint32_t tbcr; /* Global timer base count register */ - int n_IRQ; - bool qemu_timer_active; /* Is the qemu_timer is runni= ng? */ - struct QEMUTimer *qemu_timer; - struct OpenPICState *opp; /* Device timer is part of. */ - /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last - current_count written or read, only defined if qemu_timer_active. */ - uint64_t origin_time; -} OpenPICTimer; - -typedef struct OpenPICMSI { - uint32_t msir; /* Shared Message Signaled Interrupt Register */ -} OpenPICMSI; - -typedef struct IRQDest { - int32_t ctpr; /* CPU current task priority */ - IRQQueue raised; - IRQQueue servicing; - qemu_irq *irqs; - - /* Count of IRQ sources asserting on non-INT outputs */ - uint32_t outputs_active[OPENPIC_OUTPUT_NB]; -} IRQDest; - -#define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) - -typedef struct OpenPICState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion mem; - - /* Behavior control */ - FslMpicInfo *fsl; - uint32_t model; - uint32_t flags; - uint32_t nb_irqs; - uint32_t vid; - uint32_t vir; /* Vendor identification register */ - uint32_t vector_mask; - uint32_t tfrr_reset; - uint32_t ivpr_reset; - uint32_t idr_reset; - uint32_t brr1; - uint32_t mpic_mode_mask; - - /* Sub-regions */ - MemoryRegion sub_io_mem[6]; - - /* Global registers */ - uint32_t frr; /* Feature reporting register */ - uint32_t gcr; /* Global configuration register */ - uint32_t pir; /* Processor initialization register */ - uint32_t spve; /* Spurious vector register */ - uint32_t tfrr; /* Timer frequency reporting register */ - /* Source registers */ - IRQSource src[OPENPIC_MAX_IRQ]; - /* Local registers per output pin */ - IRQDest dst[MAX_CPU]; - uint32_t nb_cpus; - /* Timer registers */ - OpenPICTimer timers[OPENPIC_MAX_TMR]; - uint32_t max_tmr; - - /* Shared MSI registers */ - OpenPICMSI msi[MAX_MSI]; - uint32_t max_irq; - uint32_t irq_ipi0; - uint32_t irq_tim0; - uint32_t irq_msi; -} OpenPICState; - static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) { set_bit(n_IRQ, q->queue); diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h index 693e981965..5eb982197d 100644 --- a/include/hw/ppc/openpic.h +++ b/include/hw/ppc/openpic.h @@ -2,10 +2,13 @@ #define OPENPIC_H =20 #include "qemu-common.h" +#include "hw/sysbus.h" #include "hw/qdev-core.h" #include "qom/cpu.h" =20 -#define TYPE_OPENPIC "openpic" +#define MAX_CPU 32 +#define MAX_MSI 8 +#define VID 0x03 /* MPIC version ID */ =20 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output = */ enum { @@ -28,4 +31,158 @@ enum { #define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \ OPENPIC_MAX_TMR) =20 +/* Raven */ +#define RAVEN_MAX_CPU 2 +#define RAVEN_MAX_EXT 48 +#define RAVEN_MAX_IRQ 64 +#define RAVEN_MAX_TMR OPENPIC_MAX_TMR +#define RAVEN_MAX_IPI OPENPIC_MAX_IPI + +/* KeyLargo */ +#define KEYLARGO_MAX_CPU 4 +#define KEYLARGO_MAX_EXT 64 +#define KEYLARGO_MAX_IPI 4 +#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) +#define KEYLARGO_MAX_TMR 0 +#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ +/* Timers don't exist but this makes the code happy... */ +#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) + +/* Interrupt definitions */ +#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ +#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ +#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ +#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ = */ +/* First doorbell IRQ */ +#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) + +typedef struct FslMpicInfo { + int max_ext; +} FslMpicInfo; + +typedef enum IRQType { + IRQ_TYPE_NORMAL =3D 0, + IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */ + IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity = */ +} IRQType; + +/* Round up to the nearest 64 IRQs so that the queue length + * won't change when moving between 32 and 64 bit hosts. + */ +#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) + +typedef struct IRQQueue { + unsigned long *queue; + int32_t queue_size; /* Only used for VMSTATE_BITMAP */ + int next; + int priority; +} IRQQueue; + +typedef struct IRQSource { + uint32_t ivpr; /* IRQ vector/priority register */ + uint32_t idr; /* IRQ destination register */ + uint32_t destmask; /* bitmap of CPU destinations */ + int last_cpu; + int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ + int pending; /* TRUE if IRQ is pending */ + IRQType type; + bool level:1; /* level-triggered */ + bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ +} IRQSource; + +#define IVPR_MASK_SHIFT 31 +#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) +#define IVPR_ACTIVITY_SHIFT 30 +#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) +#define IVPR_MODE_SHIFT 29 +#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) +#define IVPR_POLARITY_SHIFT 23 +#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) +#define IVPR_SENSE_SHIFT 22 +#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) + +#define IVPR_PRIORITY_MASK (0xFU << 16) +#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> = 16)) +#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) + +/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ +#define IDR_EP 0x80000000 /* external pin */ +#define IDR_CI 0x40000000 /* critical interrupt */ + +typedef struct OpenPICTimer { + uint32_t tccr; /* Global timer current count register */ + uint32_t tbcr; /* Global timer base count register */ + int n_IRQ; + bool qemu_timer_active; /* Is the qemu_timer is runni= ng? */ + struct QEMUTimer *qemu_timer; + struct OpenPICState *opp; /* Device timer is part of. */ + /* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last + current_count written or read, only defined if qemu_timer_active. */ + uint64_t origin_time; +} OpenPICTimer; + +typedef struct OpenPICMSI { + uint32_t msir; /* Shared Message Signaled Interrupt Register */ +} OpenPICMSI; + +typedef struct IRQDest { + int32_t ctpr; /* CPU current task priority */ + IRQQueue raised; + IRQQueue servicing; + qemu_irq *irqs; + + /* Count of IRQ sources asserting on non-INT outputs */ + uint32_t outputs_active[OPENPIC_OUTPUT_NB]; +} IRQDest; + +#define TYPE_OPENPIC "openpic" +#define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC) + +typedef struct OpenPICState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion mem; + + /* Behavior control */ + FslMpicInfo *fsl; + uint32_t model; + uint32_t flags; + uint32_t nb_irqs; + uint32_t vid; + uint32_t vir; /* Vendor identification register */ + uint32_t vector_mask; + uint32_t tfrr_reset; + uint32_t ivpr_reset; + uint32_t idr_reset; + uint32_t brr1; + uint32_t mpic_mode_mask; + + /* Sub-regions */ + MemoryRegion sub_io_mem[6]; + + /* Global registers */ + uint32_t frr; /* Feature reporting register */ + uint32_t gcr; /* Global configuration register */ + uint32_t pir; /* Processor initialization register */ + uint32_t spve; /* Spurious vector register */ + uint32_t tfrr; /* Timer frequency reporting register */ + /* Source registers */ + IRQSource src[OPENPIC_MAX_IRQ]; + /* Local registers per output pin */ + IRQDest dst[MAX_CPU]; + uint32_t nb_cpus; + /* Timer registers */ + OpenPICTimer timers[OPENPIC_MAX_TMR]; + uint32_t max_tmr; + + /* Shared MSI registers */ + OpenPICMSI msi[MAX_MSI]; + uint32_t max_irq; + uint32_t irq_ipi0; + uint32_t irq_tim0; + uint32_t irq_msi; +} OpenPICState; + #endif /* OPENPIC_H */ --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850681375123.63907079952912; Wed, 28 Feb 2018 12:44:41 -0800 (PST) Received: from localhost ([::1]:46781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8ad-0002GK-RX for importer@patchew.org; Wed, 28 Feb 2018 15:44:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Sr-0003Z5-Qq for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8Sq-0003on-Mw for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:37 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58509 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8Sq-0003nw-GQ; Wed, 28 Feb 2018 15:36:36 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pm-0003Ba-Vo; Wed, 28 Feb 2018 20:33:29 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:41 +0000 Message-Id: <20180228203243.1413-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 10/12] mac_newworld: use object link to pass OpenPIC object to macio X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also switch macio_newworld_realize() over to use it rather than using the p= ic_mem memory region directly. Now that both Old World and New World macio devices no longer make use of t= he pic_mem memory region directly, we can remove it. Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson --- hw/misc/macio/macio.c | 14 +++++++++----- hw/ppc/mac_newworld.c | 20 +++++++++++--------- include/hw/misc/macio/macio.h | 4 +++- 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index d4c1d190c4..e5288f1084 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -279,10 +279,10 @@ static void macio_newworld_realize(PCIDevice *d, Erro= r **errp) sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]); sysbus_connect_irq(sysbus_dev, 1, ns->irqs[cur_irq++]); =20 - if (s->pic_mem) { - /* OpenPIC */ - memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem); - } + /* OpenPIC */ + sysbus_dev =3D SYS_BUS_DEVICE(ns->pic); + memory_region_add_subregion(&s->bar, 0x40000, + sysbus_mmio_get_region(sysbus_dev, 0)); =20 /* IDE buses */ for (i =3D 0; i < ARRAY_SIZE(ns->ide); i++) { @@ -311,6 +311,11 @@ static void macio_newworld_init(Object *obj) =20 qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs)); =20 + object_property_add_link(obj, "pic", TYPE_OPENPIC, + (Object **) &ns->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + for (i =3D 0; i < 2; i++) { macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i); } @@ -441,7 +446,6 @@ void macio_init(PCIDevice *d, { MacIOState *macio_state =3D MACIO(d); =20 - macio_state->pic_mem =3D pic_mem; /* Note: this code is strongly inspirated from the corresponding code in PearPC */ qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency", diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 396216954e..c7960ab67a 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -154,7 +154,7 @@ static void ppc_core99_init(MachineState *machine) hwaddr kernel_base, initrd_base, cmdline_base =3D 0; long kernel_size, initrd_size; PCIBus *pci_bus; - PCIDevice *macio; + NewWorldMacIOState *macio; MACIOIDEState *macio_ide; BusState *adb_bus; MacIONVRAMState *nvr; @@ -166,7 +166,7 @@ static void ppc_core99_init(MachineState *machine) void *fw_cfg; int machine_arch; SysBusDevice *s; - DeviceState *dev; + DeviceState *dev, *pic_dev; int *token =3D g_new(int, 1); hwaddr nvram_addr =3D 0xFFF04000; uint64_t tbfreq; @@ -333,10 +333,10 @@ static void ppc_core99_init(MachineState *machine) =20 pic =3D g_new0(qemu_irq, 64); =20 - dev =3D qdev_create(NULL, TYPE_OPENPIC); - qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_KEYLARGO); - qdev_init_nofail(dev); - s =3D SYS_BUS_DEVICE(dev); + pic_dev =3D qdev_create(NULL, TYPE_OPENPIC); + qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); + qdev_init_nofail(pic_dev); + s =3D SYS_BUS_DEVICE(pic_dev); pic_mem =3D s->mmio[0].memory; k =3D 0; for (i =3D 0; i < smp_cpus; i++) { @@ -346,7 +346,7 @@ static void ppc_core99_init(MachineState *machine) } =20 for (i =3D 0; i < 64; i++) { - pic[i] =3D qdev_get_gpio_in(dev, i); + pic[i] =3D qdev_get_gpio_in(pic_dev, i); } =20 if (PPC_INPUT(env) =3D=3D PPC_FLAGS_INPUT_970) { @@ -369,7 +369,7 @@ static void ppc_core99_init(MachineState *machine) } =20 /* MacIO */ - macio =3D pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); + macio =3D NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO)); dev =3D DEVICE(macio); qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ qdev_connect_gpio_out(dev, 1, pic[0x24]); /* ESCC-B */ @@ -379,7 +379,9 @@ static void ppc_core99_init(MachineState *machine) qdev_connect_gpio_out(dev, 5, pic[0x0e]); /* IDE */ qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE DMA */ qdev_prop_set_uint64(dev, "frequency", tbfreq); - macio_init(macio, pic_mem); + object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", + &error_abort); + macio_init(PCI_DEVICE(macio), pic_mem); =20 /* We only emulate 2 out of 3 IDE controllers for now */ ide_drive_get(hd, ARRAY_SIZE(hd)); diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h index 843c114c07..4528282b36 100644 --- a/include/hw/misc/macio/macio.h +++ b/include/hw/misc/macio/macio.h @@ -29,6 +29,7 @@ #include "hw/intc/heathrow_pic.h" #include "hw/misc/macio/cuda.h" #include "hw/ppc/mac_dbdma.h" +#include "hw/ppc/openpic.h" =20 #define TYPE_MACIO "macio" #define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO) @@ -42,7 +43,6 @@ typedef struct MacIOState { CUDAState cuda; DBDMAState dbdma; ESCCState escc; - MemoryRegion *pic_mem; uint64_t frequency; } MacIOState; =20 @@ -70,6 +70,8 @@ typedef struct NewWorldMacIOState { /*< private >*/ MacIOState parent_obj; /*< public >*/ + + OpenPICState *pic; qemu_irq irqs[7]; MACIOIDEState ide[2]; } NewWorldMacIOState; --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850515378406.11716231487037; Wed, 28 Feb 2018 12:41:55 -0800 (PST) Received: from localhost ([::1]:46759 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Xx-00086x-Pw for importer@patchew.org; Wed, 28 Feb 2018 15:41:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8So-0003Uh-8x for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8Sn-0003mj-Hp for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:34 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58508 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8Sn-0003mG-Ak; Wed, 28 Feb 2018 15:36:33 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pp-0003Ba-9n; Wed, 28 Feb 2018 20:33:30 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:42 +0000 Message-Id: <20180228203243.1413-12-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 11/12] macio: move setting of CUDA timebase frequency to macio_common_realize() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This removes the last of the functionality from macio_init() in preparation for its subsequent removal. Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson --- hw/misc/macio/macio.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index e5288f1084..f71ed61819 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -101,6 +101,8 @@ static void macio_common_realize(PCIDevice *d, Error **= errp) memory_region_add_subregion(&s->bar, 0x08000, sysbus_mmio_get_region(sysbus_dev, 0)); =20 + qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency", + s->frequency); object_property_set_bool(OBJECT(&s->cuda), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -444,12 +446,7 @@ type_init(macio_register_types) void macio_init(PCIDevice *d, MemoryRegion *pic_mem) { - MacIOState *macio_state =3D MACIO(d); - /* Note: this code is strongly inspirated from the corresponding code in PearPC */ - qdev_prop_set_uint64(DEVICE(&macio_state->cuda), "timebase-frequency", - macio_state->frequency); - qdev_init_nofail(DEVICE(d)); } --=20 2.11.0 From nobody Wed Oct 22 04:24:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519850765828219.21327430158408; Wed, 28 Feb 2018 12:46:05 -0800 (PST) Received: from localhost ([::1]:46798 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8by-0003Wd-La for importer@patchew.org; Wed, 28 Feb 2018 15:46:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1er8Sn-0003Tn-8h for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1er8Sk-0003lT-4x for qemu-devel@nongnu.org; Wed, 28 Feb 2018 15:36:33 -0500 Received: from chuckie.co.uk ([82.165.15.123]:58505 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1er8Sj-0003lA-Tn; Wed, 28 Feb 2018 15:36:30 -0500 Received: from host109-151-5-120.range109-151.btcentralplus.com ([109.151.5.120] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1er8Pq-0003Ba-HG; Wed, 28 Feb 2018 20:33:31 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Wed, 28 Feb 2018 20:32:43 +0000 Message-Id: <20180228203243.1413-13-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> References: <20180228203243.1413-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.151.5.120 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCHv3 12/12] macio: remove macio_init() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the remaining comment into macio.c for reference, then remove the macio_init() function and instantiate the macio devices for both Old World and New World machines via qdev_init_nofail() directly. Signed-off-by: Mark Cave-Ayland --- hw/misc/macio/macio.c | 11 +++-------- hw/ppc/mac_newworld.c | 4 +--- hw/ppc/mac_oldworld.c | 4 +--- 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index f71ed61819..af1bd46b4b 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -33,6 +33,9 @@ #include "hw/misc/macio/macio.h" #include "hw/intc/heathrow_pic.h" =20 +/* Note: this code is strongly inspirated from the corresponding code + * in PearPC */ + /* * The mac-io has two interfaces to the ESCC. One is called "escc-legacy", * while the other one is the normal, current ESCC interface. @@ -442,11 +445,3 @@ static void macio_register_types(void) } =20 type_init(macio_register_types) - -void macio_init(PCIDevice *d, - MemoryRegion *pic_mem) -{ - /* Note: this code is strongly inspirated from the corresponding code - in PearPC */ - qdev_init_nofail(DEVICE(d)); -} diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index c7960ab67a..a749e2565d 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -160,7 +160,6 @@ static void ppc_core99_init(MachineState *machine) MacIONVRAMState *nvr; int bios_size, ndrv_size; uint8_t *ndrv_file; - MemoryRegion *pic_mem; int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; void *fw_cfg; @@ -337,7 +336,6 @@ static void ppc_core99_init(MachineState *machine) qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); qdev_init_nofail(pic_dev); s =3D SYS_BUS_DEVICE(pic_dev); - pic_mem =3D s->mmio[0].memory; k =3D 0; for (i =3D 0; i < smp_cpus; i++) { for (j =3D 0; j < OPENPIC_OUTPUT_NB; j++) { @@ -381,7 +379,7 @@ static void ppc_core99_init(MachineState *machine) qdev_prop_set_uint64(dev, "frequency", tbfreq); object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", &error_abort); - macio_init(PCI_DEVICE(macio), pic_mem); + qdev_init_nofail(dev); =20 /* We only emulate 2 out of 3 IDE controllers for now */ ide_drive_get(hd, ARRAY_SIZE(hd)); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 3ac5b19073..935493c966 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -96,7 +96,6 @@ static void ppc_heathrow_init(MachineState *machine) OldWorldMacIOState *macio; MACIOIDEState *macio_ide; DeviceState *dev, *pic_dev; - SysBusDevice *sbd; BusState *adb_bus; int bios_size, ndrv_size; uint8_t *ndrv_file; @@ -283,8 +282,7 @@ static void ppc_heathrow_init(MachineState *machine) qdev_prop_set_uint64(dev, "frequency", tbfreq); object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", &error_abort); - sbd =3D SYS_BUS_DEVICE(pic_dev); - macio_init(PCI_DEVICE(macio), sysbus_mmio_get_region(sbd, 0)); + qdev_init_nofail(dev); =20 macio_ide =3D MACIO_IDE(object_resolve_path_component(OBJECT(macio), "ide[0]")); --=20 2.11.0