From nobody Tue Feb 10 05:46:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519742635812511.69639735986425; Tue, 27 Feb 2018 06:43:55 -0800 (PST) Received: from localhost ([::1]:37687 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgTw-0007cF-Id for importer@patchew.org; Tue, 27 Feb 2018 09:43:52 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55764) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgPJ-0003d3-Kk for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqgPI-0007yX-08 for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:05 -0500 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:38865) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqgPH-0007yB-M1 for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:03 -0500 Received: by mail-wr0-x241.google.com with SMTP id n7so25120068wrn.5 for ; Tue, 27 Feb 2018 06:39:03 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m55sm13757785wrf.38.2018.02.27.06.38.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 06:38:59 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 410D23E0962; Tue, 27 Feb 2018 14:38:53 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LJUErzFkgq9BGjZ2PKmulrYADuCBwuUQ20W84XZ+HPc=; b=cwnTELqLYnNynVfzLquAzfiEp6Kgr0ciFSZRA7WepPxXj32qA9fQ41Lsu6XG+SpFTI M3p7VNdkPbhouMsgUxpACHpdDrNEZp2rt7auAAe3hsY+nQhZWTrr7jKvPWTA5rr3V1U+ ruk2x8ScZ+CrNFKJratBTNpRL65gSHY+CG9Oo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LJUErzFkgq9BGjZ2PKmulrYADuCBwuUQ20W84XZ+HPc=; b=T7My6Gi4KiaUabLbOQG4tKCcrscqrF5zyvtLfAWTpTsY7Z8puhNskfYna1KY4S2TSM 3iqtHPqTxz2Q0QHCinRv3Pg+zWQN2XezXeoAiESM+vbkIZPqNwd7fW6t+udAmnTEVMFN KxR6XDvnii/lbzuSHFsIpHl7c5ld+dLrCqL+PkM5woy7WpWSuhB6xHdwJhUAjH53W3OX 8HSPoAhLFb0dsH8YiPwSkWMT666WxT+ud3lCg0wvB6h6jZ83EsFo4GHCpjEaYX3c8tJx dZg3k4SU4eI/M8oWIEjl7rRvIwhJycVOYjBA4CjJdHCt1p/UbLZjxGT5vTjCb/f2SItA Kx/A== X-Gm-Message-State: APf1xPDLlAYqVJPF553FBYRQudejWCZwkvWOFLXjd9YhIicnbtGpqTwV O0MGY32MmJbBqWgM3F/yMLmorA== X-Google-Smtp-Source: AH8x2272wmpp+5qOvfDoQPxxhUUHbC7+wlrTKT0aNVTwYLo0Zggx9IkJnAr9HGIWiiX02Y2jnjYjtw== X-Received: by 10.223.178.232 with SMTP id g95mr13946311wrd.35.1519742342469; Tue, 27 Feb 2018 06:39:02 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Tue, 27 Feb 2018 14:38:26 +0000 Message-Id: <20180227143852.11175-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180227143852.11175-1-alex.bennee@linaro.org> References: <20180227143852.11175-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v4 05/31] target/arm/helper: pass explicit fpst to set_rmode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++-- target/arm/helper.h | 2 +- target/arm/translate-a64.c | 26 +++++++++++++------------- target/arm/translate.c | 12 ++++++------ 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f450eb200f..303cd1eaf9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11393,9 +11393,9 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ -uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) +uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) { - float_status *fp_status =3D &env->vfp.fp_status; + float_status *fp_status =3D fpstp; =20 uint32_t prev_rmode =3D get_float_rounding_mode(fp_status); set_float_rounding_mode(rmode, fp_status); diff --git a/target/arm/helper.h b/target/arm/helper.h index 6383d7d09e..81ecb319b3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -167,7 +167,7 @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) =20 -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env) +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) =20 DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2c64d2b3fe..91c2b8ed11 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4628,10 +4628,10 @@ static void handle_fp_1src_single(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -4687,10 +4687,10 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -5217,7 +5217,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); =20 if (is_double) { TCGv_i64 tcg_double =3D read_fp_dreg(s, rn); @@ -5264,7 +5264,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); =20 if (!sf) { @@ -6984,8 +6984,8 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_shift =3D tcg_const_i32(fracbits); =20 if (is_double) { @@ -7029,7 +7029,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, =20 tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_shift); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } =20 @@ -8300,8 +8300,8 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) =20 if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; tcg_fpstatus =3D NULL; @@ -8366,7 +8366,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) } =20 if (is_fcvt) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(tcg_fpstatus); } @@ -10680,14 +10680,14 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) return; } =20 - if (need_fpstatus) { + if (need_fpstatus || need_rmode) { tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_fpstatus =3D NULL; } if (need_rmode) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; } @@ -10929,7 +10929,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) clear_vec_high(s, is_q, rd); =20 if (need_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } if (need_fpstatus) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 1270022289..aa6dcaa577 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3143,7 +3143,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, TCGv_i32 tcg_rmode; =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_op; @@ -3167,7 +3167,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_res); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_ptr(fpst); @@ -3184,7 +3184,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_shift =3D tcg_const_i32(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_double, tcg_res; @@ -3222,7 +3222,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_i32(tcg_shift); @@ -3892,13 +3892,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) TCGv_ptr fpst =3D get_fpstatus_ptr(0); TCGv_i32 tcg_rmode; tcg_rmode =3D tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); } else { gen_helper_rints(cpu_F0s, cpu_F0s, fpst); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(fpst); break; --=20 2.15.1