From nobody Mon Feb 9 23:02:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519743471128832.0639051224316; Tue, 27 Feb 2018 06:57:51 -0800 (PST) Received: from localhost ([::1]:37795 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqghR-0003JM-TG for importer@patchew.org; Tue, 27 Feb 2018 09:57:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58513) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgYD-0003gF-LG for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqgY9-0001on-Uy for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:17 -0500 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:46039) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqgY9-0001kq-IF for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:13 -0500 Received: by mail-wr0-x242.google.com with SMTP id p104so25107917wrc.12 for ; Tue, 27 Feb 2018 06:48:13 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y34sm27892743wry.19.2018.02.27.06.48.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 06:48:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 7D2053E1615; Tue, 27 Feb 2018 14:38:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2e7aJXQxh9u/kBr+CG6HEHolwVuMtqX68/ZiwUSBI0c=; b=CqbEJ+UNYvwxmQhoiFPW6A0d5cKSeVLWv/UDElWx5Sz0TXzmkKLI0yWAHAaUp8Imo3 MMWXgY19pzTqtH4KVd4SSXQd3avi188E5frMLKBvEO+GzRc3fzs4qox/CkILv038LLNE DJvJjsVH+00S3/URFUpq0IfExViw+a31kJXiE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2e7aJXQxh9u/kBr+CG6HEHolwVuMtqX68/ZiwUSBI0c=; b=jgDIvLsoeZ64lx000C6I+Q2SaEbdzaKdoWlBrMilxOCcvGxQeMcFbReMw1INj9EgwO VTnE4dBriIUIHAbDXGununoKeixaCQJU4E/6UYY6xZlveYZq8hs1KEiToMYzO1SDFmhQ sj2d2wivn8SY9YGdY288bay/VRLalitEOUbfF9afkXdQT3Q7K99J0MXdaIFAOLwkXIK9 RAOmlf4HfDncFwMRc/ZMici8ENuBzrxKtUu8Hj3wFNQlBaIlQQ42mvRNgVm4VTSt/DK7 TSUdOA+QUJkMHB8XqmSLyTI6uQWLqkfh/trIQclLhtHdVjK8t/32HMhyJwuBbBW6cBMX 7sng== X-Gm-Message-State: APf1xPAq/eCdVzedB7RYAmZLzILThyURwfqZl55bcHHtEzkGjYs7YN3M h+TZ5nLtogc0ETbvhB+sYkKA7g== X-Google-Smtp-Source: AH8x226N2CiaefBgsPGdN2Lj32FjK0i7pmeb4Q9t7tBi1zMiMhY+m525Z0xriZDm1cNnSKsMpZLcUg== X-Received: by 10.223.138.130 with SMTP id y2mr12074227wry.242.1519742892356; Tue, 27 Feb 2018 06:48:12 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Tue, 27 Feb 2018 14:38:42 +0000 Message-Id: <20180227143852.11175-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180227143852.11175-1-alex.bennee@linaro.org> References: <20180227143852.11175-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - fixup re-base conflicts - make both operations pure bitwise TCG --- target/arm/translate-a64.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6f33783a11..9f2c3682dc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) TCGv_i32 tcg_rmode =3D NULL; TCGv_ptr tcg_fpstatus =3D NULL; bool need_rmode =3D false; + bool need_fpst =3D true; int rmode; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { @@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) need_rmode =3D true; rmode =3D FPROUNDING_ZERO; break; + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + need_fpst =3D false; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) return; } =20 - if (need_rmode) { + if (need_rmode || need_fpst) { tcg_fpstatus =3D get_fpstatus_ptr(true); } =20 @@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } @@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) case 0x59: /* FRINTX */ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstat= us); break; + case 0x2f: /* FABS */ + tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); + break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } --=20 2.15.1