From nobody Tue Feb 10 03:16:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151974411823590.9133421920485; Tue, 27 Feb 2018 07:08:38 -0800 (PST) Received: from localhost ([::1]:37874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgrs-0003ku-RY for importer@patchew.org; Tue, 27 Feb 2018 10:08:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgYD-0003g7-Jf for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqgY9-0001lI-4e for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:17 -0500 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:35656) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqgY8-0001hS-LT for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:48:12 -0500 Received: by mail-wr0-x242.google.com with SMTP id l43so25176430wrc.2 for ; Tue, 27 Feb 2018 06:48:12 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id a67sm27138299wrc.13.2018.02.27.06.48.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 06:48:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 6BB113E15E1; Tue, 27 Feb 2018 14:38:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WW5W8z9MItaE0KqpoYIgIPEx/0pUcIrykYOR6JKcE1s=; b=IvpcYGd2SEVes5jUWHkyeAsuQkz/EZPK2NsqJUnX5LMOFwhjQDKRkvarv5SR3Xxlg7 I3P6R++vOopruqtWQwBLed+p7H1iyEj5Jbmpc6UdCdt5denoJrcdRXzmSvPbHsOFFr8W gIVZ5nb/I6Nlq9Z1XwsPy5uDlQRVGjJNYt+3A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WW5W8z9MItaE0KqpoYIgIPEx/0pUcIrykYOR6JKcE1s=; b=C2MJJBOg4ADq3ywehOiFvwDNGtwPJesKBObfXNO7qSeeJzJw4upaEFbpvs9NVb+xEo C4rwaOjXy7FD4wrLm978kxfQmsZ1RJVjhlKK3I+jgZ/mtXg/y6g3j1NW+P2WyhBRDj2v RXMtWkiu4mWrxlp8Q1Q2B0KPKj3V6swqSjyn7NP3WjOCq3K6JNwQd6EnZGTPGvk61glF YN9Qq0br0Zwf4QS3dKt+beoba0t9dbCVFAvUFaMTe2qA1hy/wqE35nN4G11bdnpQGAK+ 6QPz78DBRR32dcNGYeGc6k9EisuFWbVa2uh1msyOmXPBWaISIIEwHwF+kloIcXrCcdmU gCcA== X-Gm-Message-State: APf1xPAU5Shf2NfU9ngnUGBsgcbq40TQS72csuaCiNoCahVLyTFTHAvp Pc4carSXfWlkL5goF4sPiqtyEQ== X-Google-Smtp-Source: AH8x227rAjHsZVaTKi8xIfYhLjTO9bb5oBfBGMYpawo5V1LkGz8F17tg0AaCuozKi2k+oljAMBhnTA== X-Received: by 10.223.136.44 with SMTP id d41mr13630048wrd.127.1519742891315; Tue, 27 Feb 2018 06:48:11 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Tue, 27 Feb 2018 14:38:41 +0000 Message-Id: <20180227143852.11175-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180227143852.11175-1-alex.bennee@linaro.org> References: <20180227143852.11175-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v4 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++ target/arm/helper.h | 10 ++++ target/arm/translate-a64.c | 114 +++++++++++++++++++++++++++++++++++------= ---- 3 files changed, 104 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 303cd1eaf9..6e3dadb754 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11302,8 +11302,10 @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \ CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) =20 +FLOAT_CONVS(si, h, 16, ) FLOAT_CONVS(si, s, 32, ) FLOAT_CONVS(si, d, 64, ) +FLOAT_CONVS(ui, h, 16, u) FLOAT_CONVS(ui, s, 32, u) FLOAT_CONVS(ui, d, 64, u) =20 @@ -11386,6 +11388,8 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) VFP_CONV_FIX(uh, s, 32, 32, uint16) VFP_CONV_FIX(ul, s, 32, 32, uint32) VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) +VFP_CONV_FIX_A64(sl, h, 16, 32, int32) +VFP_CONV_FIX_A64(ul, h, 16, 32, uint32) #undef VFP_CONV_FIX #undef VFP_CONV_FIX_FLOAT #undef VFP_CONV_FLOAT_FIX_ROUND diff --git a/target/arm/helper.h b/target/arm/helper.h index 81ecb319b3..c0f35592ff 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -120,17 +120,23 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) =20 +DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, ptr) DEF_HELPER_2(vfp_uitod, f64, i32, ptr) +DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) DEF_HELPER_2(vfp_sitos, f32, i32, ptr) DEF_HELPER_2(vfp_sitod, f64, i32, ptr) =20 +DEF_HELPER_2(vfp_touih, i32, f16, ptr) DEF_HELPER_2(vfp_touis, i32, f32, ptr) DEF_HELPER_2(vfp_touid, i32, f64, ptr) +DEF_HELPER_2(vfp_touizh, i32, f16, ptr) DEF_HELPER_2(vfp_touizs, i32, f32, ptr) DEF_HELPER_2(vfp_touizd, i32, f64, ptr) +DEF_HELPER_2(vfp_tosih, i32, f16, ptr) DEF_HELPER_2(vfp_tosis, i32, f32, ptr) DEF_HELPER_2(vfp_tosid, i32, f64, ptr) +DEF_HELPER_2(vfp_tosizh, i32, f16, ptr) DEF_HELPER_2(vfp_tosizs, i32, f32, ptr) DEF_HELPER_2(vfp_tosizd, i32, f64, ptr) =20 @@ -142,6 +148,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, pt= r) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) @@ -166,6 +174,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) =20 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c02f1e23c..6f33783a11 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6902,23 +6902,28 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, int elements, int is_signed, int fracbits, int size) { - bool is_double =3D size =3D=3D 3 ? true : false; - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); - TCGv_i32 tcg_shift =3D tcg_const_i32(fracbits); - TCGv_i64 tcg_int =3D tcg_temp_new_i64(); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + TCGv_i32 tcg_shift =3D NULL; + TCGMemOp mop =3D size | (is_signed ? MO_SIGN : 0); int pass; =20 - for (pass =3D 0; pass < elements; pass++) { - read_vec_element(s, tcg_int, rn, pass, mop); + if (fracbits || size =3D=3D MO_64) { + tcg_shift =3D tcg_const_i32(fracbits); + } + + if (size =3D=3D MO_64) { + TCGv_i64 tcg_int64 =3D tcg_temp_new_i64(); + TCGv_i64 tcg_double =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < elements; pass++) { + read_vec_element(s, tcg_int64, rn, pass, mop); =20 - if (is_double) { - TCGv_i64 tcg_double =3D tcg_temp_new_i64(); if (is_signed) { - gen_helper_vfp_sqtod(tcg_double, tcg_int, + gen_helper_vfp_sqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } else { - gen_helper_vfp_uqtod(tcg_double, tcg_int, + gen_helper_vfp_uqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } if (elements =3D=3D 1) { @@ -6926,28 +6931,72 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, } else { write_vec_element(s, tcg_double, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single =3D tcg_temp_new_i32(); - if (is_signed) { - gen_helper_vfp_sqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); - } else { - gen_helper_vfp_uqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); + } + + tcg_temp_free_i64(tcg_int64); + tcg_temp_free_i64(tcg_double); + + } else { + TCGv_i32 tcg_int32 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_float =3D tcg_temp_new_i32(); + + for (pass =3D 0; pass < elements; pass++) { + read_vec_element_i32(s, tcg_int32, rn, pass, mop); + + switch (size) { + case MO_32: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fps= t); + } else { + gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fps= t); + } + } + break; + case MO_16: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fps= t); + } else { + gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fps= t); + } + } + break; + default: + g_assert_not_reached(); } + if (elements =3D=3D 1) { - write_fp_sreg(s, rd, tcg_single); + write_fp_sreg(s, rd, tcg_float); } else { - write_vec_element_i32(s, tcg_single, rd, pass, MO_32); + write_vec_element_i32(s, tcg_float, rd, pass, size); } - tcg_temp_free_i32(tcg_single); } + + tcg_temp_free_i32(tcg_int32); + tcg_temp_free_i32(tcg_float); } =20 - tcg_temp_free_i64(tcg_int); tcg_temp_free_ptr(tcg_fpst); - tcg_temp_free_i32(tcg_shift); + if (tcg_shift) { + tcg_temp_free_i32(tcg_shift); + } =20 clear_vec_high(s, elements << size =3D=3D 16, rd); } @@ -11236,6 +11285,23 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) rn =3D extract32(insn, 5, 5); =20 switch (fpop) { + case 0x1d: /* SCVTF */ + case 0x5d: /* UCVTF */ + { + int elements; + + if (is_scalar) { + elements =3D 1; + } else { + elements =3D (is_q ? 8 : 4); + } + + if (!fp_access_check(s)) { + return; + } + handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); + return; + } break; case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ --=20 2.15.1