From nobody Tue Feb 10 02:54:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519742864669657.1467551168067; Tue, 27 Feb 2018 06:47:44 -0800 (PST) Received: from localhost ([::1]:37718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgXf-0002m4-FF for importer@patchew.org; Tue, 27 Feb 2018 09:47:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55968) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eqgPR-0003lQ-W1 for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eqgPQ-00083j-CF for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:13 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:35973) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eqgPP-00082l-VG for qemu-devel@nongnu.org; Tue, 27 Feb 2018 09:39:12 -0500 Received: by mail-wm0-x243.google.com with SMTP id 188so23613694wme.1 for ; Tue, 27 Feb 2018 06:39:11 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 78sm10437782wmb.25.2018.02.27.06.38.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 06:39:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 46B163E0CC8; Tue, 27 Feb 2018 14:38:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SYe81JmCa69AGdz9POFr4xojLPka4BisynWWhclkIAo=; b=G+mgGkAb8iz5V6a06nIfGYNNOHN9CvAvhE6BqqMkjQiU27vemZIZ1RhlVE8TW+374d DI5YRcSA5W36Jy9As/N3hiG8iIbpGXkSTmVWmV0khqjrrZyQvykDOm9fQ4Gedv5ihvSJ kxx7UBUmFgHUf3zAV6EImUHSqRpkfGf/NgIWA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SYe81JmCa69AGdz9POFr4xojLPka4BisynWWhclkIAo=; b=cx7TEUEOHujhRM+akhBHNIg0sAWT5UBuMAFPW8AiDDwiggshgZLR7BD2iUhcSc8L+q 4b3fhjEMAZbqT+0Ci7Bkmt5Q1CXpRmypQm3xZD3Gz7d66rIotHJbwAltos3HFfq8dQLT h3kJGte1I0Yp7xJRxwCAJpEGCnWZUT9LiMdst0342UTp0xaLgdPvNxKIAQcKV2cFcOv2 dJgSADP9IZOC1+vcXohPOgj1yOja69E0wvSraTZJUVLgWC0JVKf3FhuWff29/2oz3gQt CuNeR44EEfYZHf62oBgEJTEW5E1j5c4nBMp8Kxvj/micKr+ZSF32pfmGvIyeiwAPpQi9 weZw== X-Gm-Message-State: APf1xPAEJxMiMGjjOOJiQJhXE+WD58Ds6z8NoodAJajYkTX8HgnOSnpM 5n+njj/qonso4cN+TnAm1Zqc3Q== X-Google-Smtp-Source: AG47ELu9I8b2RxcdgOuJxfFYyBnCByi/Gaezw0yF8KP5codPIOcP9n/I798ByE+KHTQe7eFrqTicyQ== X-Received: by 10.28.6.83 with SMTP id 80mr5953071wmg.12.1519742350788; Tue, 27 Feb 2018 06:39:10 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Tue, 27 Feb 2018 14:38:39 +0000 Message-Id: <20180227143852.11175-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180227143852.11175-1-alex.bennee@linaro.org> References: <20180227143852.11175-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v4 18/31] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This covers all the floating point convert operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 32 +++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 85 ++++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4fd28fdf48..722fff2349 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -767,3 +767,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_stat= us) =20 return ret; } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} + +uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_uint16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index bc8d5b105b..32931b17c6 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -77,3 +77,5 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) +DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3c37eb99ff..046079b1b3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11240,6 +11240,46 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) only_in_vector =3D true; /* current rounding mode */ break; + case 0x1a: /* FCVTNS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x1b: /* FCVTMS */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x1c: /* FCVTAS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x3a: /* FCVTPS */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x3b: /* FCVTZS */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; + case 0x5a: /* FCVTNU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x5b: /* FCVTMU */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x5c: /* FCVTAU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x7a: /* FCVTPU */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x7b: /* FCVTZU */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11273,7 +11313,36 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - /* no operations yet */ + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, 0, MO_16); + + switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + /* limit any sign extension going on */ + tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); } else { for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); @@ -11282,6 +11351,20 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); =20 switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ --=20 2.15.1