From nobody Fri Oct 24 09:45:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400671416589.4515835280727; Fri, 23 Feb 2018 07:44:31 -0800 (PST) Received: from localhost ([::1]:45277 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFWQ-0001Fs-Fi for importer@patchew.org; Fri, 23 Feb 2018 10:44:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFOz-0002oB-1E for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFOx-0007A6-TR for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:49 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:36510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFOx-00078B-LQ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:47 -0500 Received: by mail-wr0-x243.google.com with SMTP id v111so2300746wrb.3 for ; Fri, 23 Feb 2018 07:36:47 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id w31sm3715921wrc.49.2018.02.23.07.36.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 1D1DB3E055F; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5e92OlfPhH3uuKn8l58mdAFexdWXszJjfX8UyDvWKY8=; b=N7P/6L3ZiOMtrUsFsO2iJaBM1EA+7WOc5XEnm6Tyc3Ch5cjx/jkf2Q/KTzrV4sqTd/ RewVzodMrXVzbniCnsBp4xUSe96ub0SxcpEksunTKWoSiY9pnL6cxsYgaRIe/toIkXaK nzy+jkhk7DHLfDTEkV6ZlwjutzDLkmak2tx5c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5e92OlfPhH3uuKn8l58mdAFexdWXszJjfX8UyDvWKY8=; b=WH4UXPTKCt4VVqSHlSwxKRUCJm0QgYycPLNltJt4dkhZCVI/Pmm+V79FPQs+glh6Q6 irkCOrLshkSdK25iE5A/Y3FFrOibBvAMQ1nozLiJgnAQAVmo8SqwZrqzxfu+CJ9btOx/ 6dnwo4HBiYzOKE9ZXboBHlmUqbTum4hEE83XxcQRVY62l8w7bVdJ4Sw8JDFLRx9jc7Tn aJi3wHv93dtXZ+Ajh3iuk/PBtelRgHeM6KYwgNclvI3c6oZpQPQ0wh3GKQ4mhGqohCHH 0LW6KcKm3Wc5NJrvLJLuAwskGgiWcR2bEeEyz7Vo2E8bYUtvvQgE0mQ9ewpqe9rGu0jA kyDw== X-Gm-Message-State: APf1xPDtkTuNxXiBRHpzn1tJV3GRVS1Pw32HCeAMaMx25rwslZRDvO43 xw0LSPkqOi+VUoH7mLT/v+e3qA== X-Google-Smtp-Source: AH8x226HrISEfDjGrT0RNuXQSYxh5/d9t1xbCVNfxhI+uuSIbRZZ0g/qML/KpKrruv1/xRhqDR5CsA== X-Received: by 10.223.178.232 with SMTP id g95mr2188451wrd.35.1519400206541; Fri, 23 Feb 2018 07:36:46 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:13 +0000 Message-Id: <20180223153636.29809-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5dd54b7ac4..4828457b5b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10228,6 +10228,78 @@ static void disas_simd_three_reg_same(DisasContext= *s, uint32_t insn) } } =20 +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 = 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | R= d | + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode =3D extract32(insn, 11, 3); + u =3D extract32(insn, 29, 1); + a =3D extract32(insn, 23, 1); + is_q =3D extract32(insn, 30, 1); + rm =3D extract32(insn, 16, 5); + rn =3D extract32(insn, 5, 5); + rd =3D extract32(insn, 0, 5); + + fpopcode =3D opcode | (a << 3) | (u << 4); + datasize =3D is_q ? 128 : 64; + elements =3D datasize / 16; + + fpst =3D get_fpstatus_ptr(true); + + for (pass =3D 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + clear_vec_high(s, is_q, rd); +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11975,6 +12047,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1