From nobody Fri Oct 24 09:45:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400605519293.49746621072063; Fri, 23 Feb 2018 07:43:25 -0800 (PST) Received: from localhost ([::1]:45275 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFVM-0000At-KU for importer@patchew.org; Fri, 23 Feb 2018 10:43:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFP8-000304-GM for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFP7-0007aZ-7W for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:58 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:52089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFP6-0007Y6-Ug for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:57 -0500 Received: by mail-wm0-x244.google.com with SMTP id h21so5411809wmd.1 for ; Fri, 23 Feb 2018 07:36:56 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 10sm2420740wmj.19.2018.02.23.07.36.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:53 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id C641F3E166A; Fri, 23 Feb 2018 15:36:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tv4Zhs3o461Gy4MmZSdB/JuJ0NzfPkhDDCA0eX99/dk=; b=WEKlVMATV6IK+PhpWlvDEQMGQF9l2/opSCpWXvPPRz5zpeUizrshvPYs6tZdWZmGgt zK+tbXe3X7W6Gx/zIyIqF9s5OtpG5BIcwQcM/2eV+9wpmAAzvsQDnN7W0BMGXhREWVZE +r6FZqpnEACI3Vj8c2jgpxXN4JSL6vs0qZPQw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tv4Zhs3o461Gy4MmZSdB/JuJ0NzfPkhDDCA0eX99/dk=; b=GM0chuSO4/zqHeITHFfuLXIRBOyj8qfFLWTME7vGQkFAGiP80VynPuzJhKPOdsqtWC TYmyxPVH62SBh0aeXRZagNQGGI52bKyWpPgy5C542B3u2fnjbUulVj9iLBRE/jB3GbEh jcabRzxvYvcGTRbn8SFTGkPKuJSU1hjUWlkzqKZ9gkbCnwA3LgzwWGO2aJgklc/CRNpv Q8WW6JZc0+U3Hs9IwjAjo+nDSO7xDcI252HDrPKgVnR3QHq7UVNojNhHQfQ2utbdBXHE hkL5loG6T4xw36caXamUdgRpnyqt4mE65ImSEkFRxOqBodfWLd8BiBLYwgPUmOQjzre/ YCNQ== X-Gm-Message-State: APf1xPBwSgxIysCwNs3Nuy2OxHzj39dj2YCl5sTxttbb+AdZoKx4ecAW 9MpV0mEWE8W7KYDASz+t3iH08g== X-Google-Smtp-Source: AH8x225Zfa4IKEeJy6BEiM+kGDGjKLmbjTxvQ7yA1qzLvT3iyNWkaQmTGYxmCTNvE2Sn38mZt9k8fQ== X-Received: by 10.28.164.196 with SMTP id n187mr1896778wme.141.1519400215816; Fri, 23 Feb 2018 07:36:55 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:35 +0000 Message-Id: <20180223153636.29809-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This covers the encoding group: Advanced SIMD scalar three same FP16 As all the helpers are already there it is simply a case of calling the existing helpers in the scalar context. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes v3 - check for FP16 feature - remove stray debug - make abs a bitwise operation - checkpatch long line --- target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6eae8bd8b1..6704d66be7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7802,6 +7802,104 @@ static void disas_simd_scalar_three_reg_same(DisasC= ontext *s, uint32_t insn) tcg_temp_free_i64(tcg_rd); } =20 +/* AdvSIMD scalar three same FP16 + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * v: 0101 1110 0100 0000 0000 0100 0000 0000 =3D> 5e400400 + * m: 1101 1111 0110 0000 1100 0100 0000 0000 =3D> df60c400 + */ +static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, + uint32_t insn) +{ + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 3); + int rm =3D extract32(insn, 16, 5); + bool u =3D extract32(insn, 29, 1); + bool a =3D extract32(insn, 23, 1); + int fpopcode =3D opcode | (a << 3) | (u << 4); + TCGv_ptr fpst; + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + + switch (fpopcode) { + case 0x03: /* FMULX */ + case 0x04: /* FCMEQ (reg) */ + case 0x07: /* FRECPS */ + case 0x0f: /* FRSQRTS */ + case 0x14: /* FCMGE (reg) */ + case 0x15: /* FACGE */ + case 0x1a: /* FABD */ + case 0x1c: /* FCMGT (reg) */ + case 0x1d: /* FACGT */ + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + } + + if (!fp_access_check(s)) { + return; + } + + fpst =3D get_fpstatus_ptr(true); + + tcg_op1 =3D tcg_temp_new_i32(); + tcg_op2 =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); + read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); + + switch (fpopcode) { + case 0x03: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x04: /* FCMEQ (reg) */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x07: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x0f: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x14: /* FCMGE (reg) */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); + break; + case 0x1c: /* FCMGT (reg) */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_ptr(fpst); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -12654,6 +12752,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1