From nobody Fri Oct 24 09:43:23 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401224504116.48026688953541; Fri, 23 Feb 2018 07:53:44 -0800 (PST) Received: from localhost ([::1]:45349 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFfL-0001RU-Lg for importer@patchew.org; Fri, 23 Feb 2018 10:53:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFP7-0002yP-A4 for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFP6-0007Xi-9h for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:57 -0500 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:35695) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFP6-0007Vo-2Q for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:56 -0500 Received: by mail-wm0-x243.google.com with SMTP id x7so3054994wmc.0 for ; Fri, 23 Feb 2018 07:36:55 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id r136sm2163118wmf.18.2018.02.23.07.36.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:53 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B56AC3E0BFD; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OZrWiLY2PIzhGI7ld0ooCrCV5Vdo1gHa5ek8fcftp7g=; b=H2xrIPYHnw5nwQlql6EHs0Cra6EAV7hqHaL8TInmRPNfNqCCAJcEORcSWy4txe0BL6 Sv/fSdzko0omGbuKPHSdMILaSxgrugyBmlYJar5CzMCj/tsIXcaesGqEYayKa8PmkpSh hIyCoCJMX6UufQ2qj2fH5J75RO9PKCJiIdw8Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OZrWiLY2PIzhGI7ld0ooCrCV5Vdo1gHa5ek8fcftp7g=; b=apg8yqhKjN6ru0TgxEdfjy4yQBRJACnKG+7X8kfl+22eobqw11bz4/5nWp7SD2bbpS u9749wPa0VLocL78n+ZAH+CmsNQkKFw+qDUrQISzISdakFMm3CInrFjTqRwnVFzYm+gc fe0vI7pSU7rSDrBlIsK7ZPk64XdB2lwH981TkoG4GGf1FKy5OS2WsF62YkjtAQaTUEE5 5s5JaeWz6FZLwV8LREKsEMv2HPgjHhVoMTt4BjHZJ+8fRbGiS9XFNc47DFanU8zgZtvL mbrtCDn7Jz0xXED5k6LEnn7yS2uKhOjKCJGMiBfdwof1KQA7MFOhCtVtVtyQMFQ9PDit oOCA== X-Gm-Message-State: APf1xPDHzMSxBH3w7kACew7vR50OiaAhf1P2oCrAsKkudCbFEqI4qpV3 Gqk0viaq1397lRCXOBimkbOwzw== X-Google-Smtp-Source: AH8x2268s0k4S/rs1ZhQMIbLhFXI5NS2fHzF1ihewwmHfLuuWWysqTixwRsnN0tXHyki5as71s5MiA== X-Received: by 10.28.52.4 with SMTP id b4mr2289266wma.90.1519400214922; Fri, 23 Feb 2018 07:36:54 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:21 +0000 Message-Id: <20180223153636.29809-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions are only available in the vector form. This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch cleanups v3 - update comment on group from following patches. - rm left over debug fpf --- target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 081619a389..ea453fb6d9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11164,6 +11164,45 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } } =20 +/* AdvSIMD [scalar] two register miscellaneous (FP16) + * + * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 = 0 + * +---+---+---+---+---------+---+-------------+--------+-----+------+----= --+ + * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd= | + * +---+---+---+---+---------+---+-------------+--------+-----+------+----= --+ + * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 + * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 + * + * This actually covers two groups where scalar access is governed by + * bit 28. A bunch of the instructions (float to integral) only exist + * in the vector form and are un-allocated for the scalar decode. Also + * in the scalar decode Q is always 1. + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode =3D extract32(insn, 12, 4); + a =3D extract32(insn, 23, 1); + fpop =3D deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+-----= -+ @@ -12237,6 +12276,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1