From nobody Fri Oct 24 09:43:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400659372828.6494255748988; Fri, 23 Feb 2018 07:44:19 -0800 (PST) Received: from localhost ([::1]:45276 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFW9-0000xf-4v for importer@patchew.org; Fri, 23 Feb 2018 10:44:13 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFP3-0002t0-4W for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFP0-0007Go-IY for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:53 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:54568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFP0-0007Ee-8C for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:50 -0500 Received: by mail-wm0-x242.google.com with SMTP id z81so5393414wmb.4 for ; Fri, 23 Feb 2018 07:36:50 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g7sm2831850wrb.78.2018.02.23.07.36.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 445CA3E076E; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aMF5EFMIfmgDHcAcUtJQ+mMjaKQoI6swhZLrjQq1RZc=; b=NyR+MomhnrjQr5MO1+D1KoVRmEKghu3W+XST5LAA8DqcCC0wLi5hfxg/0lF1PjM1R4 61FTjfKmZZwobQYijaNLsAzbs+UXPi7cnrOmUbxPQHco9/fQVUPqGAdqFJncrYwu+swS 1GVTn288OrJ2eWMf/5cFJprKFCaEUqL8SiLRI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aMF5EFMIfmgDHcAcUtJQ+mMjaKQoI6swhZLrjQq1RZc=; b=HY9+qYTsg7rN8wfKCvdwgGU4/PZCoNgNMiNV+xJ9zKjlkX8d4FnH2lawP38FfWxK6G eVfbdO4dgP0AQ0TBWJ3GWBExypnNXdxyiu4smoLxUih4oGtZ06GCQWZC6bMH6l9npWp4 JzMG1ZDHFmWWPehgpWTOFVEAEvWCwLtZGx/rk19HbEBYzO9+242fgUFflpTArH57LSzq iVJDV86m9A86tIpJBLBFPjIJLbcq0qmRTN3FE+zc56tpfZYdrmKHOfRSfmliD7T5kE4x fHnNAqjdI6daxrVxBtpY6WS+rNqPCTO9bOj9efWtukiMh336Lh9eIaw8XwBmbuZ7oV+z GXJA== X-Gm-Message-State: APf1xPB492rp8glLGXHAsM2ficHv3nQqizn9klMLPq4YfiK2JvrtZF5t JZrQBzAPIG6PcV/3YkLJSwF4PA== X-Google-Smtp-Source: AG47ELtUfnTz9bW6eWnnHPiPCf5YjeiguQlB8tUzQAzlDq4ee3dXtS47ny5baZQo/emwq4huOG/JkA== X-Received: by 10.28.96.65 with SMTP id u62mr2045244wmb.82.1519400209053; Fri, 23 Feb 2018 07:36:49 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:15 +0000 Message-Id: <20180223153636.29809-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/helper-a64.h | 5 +++++ target/arm/translate-a64.c | 15 ++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 931a6d3c34..d0b284fec4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -594,3 +594,52 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* + * Floating point comparisons produce an integer result. Softfloat + * routines return float_relation types which we convert to the 0/-1 + * Neon requires. + */ + +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 + +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare_quiet(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index bac9469426..1cf40bda5e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -56,3 +56,8 @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f8770ee1e9..fb74dc1c45 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10289,6 +10289,9 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10304,6 +10307,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x17: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10311,6 +10320,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); --=20 2.15.1