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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v3 01/31] include/exec/helper-head.h: support f16 in helper calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Crosthwaite , richard.henderson@linaro.org, qemu-devel@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/exec/helper-head.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index e1fd08f2ba..15b6a68de3 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr @@ -38,6 +39,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_f16 float16 #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * @@ -94,6 +96,7 @@ #define dh_is_signed_s32 1 #define dh_is_signed_i64 0 #define dh_is_signed_s64 1 +#define dh_is_signed_f16 0 #define dh_is_signed_f32 0 #define dh_is_signed_f64 0 #define dh_is_signed_tl 0 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400502492289.3695951906592; Fri, 23 Feb 2018 07:41:42 -0800 (PST) Received: from localhost ([::1]:45261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFTU-0006iV-Sk for importer@patchew.org; Fri, 23 Feb 2018 10:41:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFOt-0002j7-LH for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFOr-0006vN-1k for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:43 -0500 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:33733) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFOq-0006si-S6 for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:40 -0500 Received: by mail-wr0-x244.google.com with SMTP id s5so14537127wra.0 for ; Fri, 23 Feb 2018 07:36:40 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id o9sm3636540wrf.43.2018.02.23.07.36.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:37 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A011E3E03B5; Fri, 23 Feb 2018 15:36:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5EXyTx7MtxQK2QtkQBD3MH1PJ+dwkjzleS7LmpbyAHo=; b=fKYlKDgsUt0mcEP5WFQ75hZ3b7s+LnIboyMHta08t7AFBzT9U1oi281RGx2iqR1wAT 3fOiKeHKukkIAih7lAyluVI9lU8Azc/BK7zAJiA1JNq78FigPeoW9HXYcVAehFDlSeUo b62OHL2kV2lQ1RyZEDY8MNmVmGFSNpn9fZmLY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5EXyTx7MtxQK2QtkQBD3MH1PJ+dwkjzleS7LmpbyAHo=; b=OjT+FMbPbc7ZGxm2b5W+WHHZU8lSZp/Rs2bDzoDJl5Ar8uqCaz/Rn2Wrd3UO3iujiY rYsh+NPVhPLBBcbiofbYPvF3R4anaW48rT7+DnN6lDYE1KrpGMe3dcMkmoG4B2k/cFl2 ELKCpBsvjnbh08rB05hR7IjtEBzKHTjVCNra2O0viVNi+NfbUfMl8j7J0Sw+RgoT2Vqi ERuqNL2BGWMUMlx//do6w8xsGUHuxob8UrsGS499vQLpDS8AY5tmOTTQlcKyeRjy2aUt CeEyQFPUxEb7iB6nCqmugzpnAaxo6Rlzs60+MjPxk6WSRJhKAtr0uKNKqQ0Su7dgtKXx wOFQ== X-Gm-Message-State: APf1xPBGgcF0ERE/o+PX6ZPdYy9ZiKkdxQi+VBSUGO0dhyowIN3D6BVE oH+A3CM6vnMuZfVX+ROdqMiywg== X-Google-Smtp-Source: AH8x224o4OBTETVotvvHzQjzgun52IDFmFPzaT9IY3SzF8PfVahbtsVJnTBw73FejSEalZx7BAHwfQ== X-Received: by 10.223.174.194 with SMTP id y60mr1965079wrc.202.1519400199695; Fri, 23 Feb 2018 07:36:39 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:07 +0000 Message-Id: <20180223153636.29809-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 02/31] target/arm/cpu64: introduce ARM_V8_FP16 feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8c839faa8f..267a9d7e2f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1408,6 +1408,7 @@ enum arm_features { ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..9743bdc8c3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ } --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 267a9d7e2f..c2bce23fa5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -168,6 +168,7 @@ typedef struct { * Qn =3D regs[n].d[1]:regs[n].d[0] * Dn =3D regs[n].d[0] * Sn =3D regs[n].d[0] bits 31..0 + * Hn =3D regs[n].d[0] bits 15..0 for even n, and bits 31..16 for odd n * * This corresponds to the architecturally defined mapping between * the two execution states, and means we do not need to explicitly --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - add FPCR_[FZ/FZ16/DN] defines to cpu.h and use - only propagate flag status to fp_status as they are ored later - ensure dnan and round mode propagated to fp_status_fp16 --- target/arm/cpu.h | 32 ++++++++++++++++++++++------ target/arm/helper.c | 26 ++++++++++++++++++----- target/arm/translate-a64.c | 53 +++++++++++++++++++++++++-----------------= ---- 3 files changed, 75 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c2bce23fa5..ebbb21391c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -538,19 +538,29 @@ typedef struct CPUARMState { /* scratch space when Tn are not sufficient. */ uint32_t scratch[8]; =20 - /* fp_status is the "normal" fp status. standard_fp_status retains - * values corresponding to the ARM "Standard FPSCR Value", ie - * default-NaN, flush-to-zero, round-to-nearest and is used by - * any operations (generally Neon) which the architecture defines - * as controlled by the standard FPSCR value rather than the FPSCR. + /* There are a number of distinct float control structures: + * + * fp_status: is the "normal" fp status. + * fp_status_fp16: used for half-precision calculations + * standard_fp_status : the ARM "Standard FPSCR Value" + * + * Half-precision operations are governed by a separate + * flush-to-zero control bit in FPSCR:FZ16. We pass a separate + * status structure to control this. + * + * The "Standard FPSCR", ie default-NaN, flush-to-zero, + * round-to-nearest and is used by any operations (generally + * Neon) which the architecture defines as controlled by the + * standard FPSCR value rather than the FPSCR. * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the two fp statuses. This relies on the + * OR of the flags in the three fp statuses. This relies on the * only thing which needs to read the exception flags being * an explicit FPSCR read. */ float_status fp_status; + float_status fp_status_f16; float_status standard_fp_status; =20 /* ZCR_EL[1-3] */ @@ -1190,12 +1200,20 @@ static inline void xpsr_write(CPUARMState *env, uin= t32_t val, uint32_t mask) uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); =20 -/* For A64 the FPSCR is split into two logically distinct registers, +/* FPCR, Floating Point Control Register + * FPSR, Floating Poiht Status Register + * + * For A64 the FPSCR is split into two logically distinct registers, * FPCR and FPSR. However since they still use non-overlapping bits * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07f79f00 + +#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ +#define FPCR_DN (1 << 25) /* Default NaN enable bit */ + static inline uint32_t vfp_get_fpsr(CPUARMState *env) { return vfp_get_fpscr(env) & FPSR_MASK; diff --git a/target/arm/helper.c b/target/arm/helper.c index c5bc69b961..f450eb200f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11103,6 +11103,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_stride << 20); i =3D get_float_exception_flags(&env->vfp.fp_status); i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + i |=3D get_float_exception_flags(&env->vfp.fp_status_f16); fpscr |=3D vfp_exceptbits_from_host(i); return fpscr; } @@ -11160,16 +11161,31 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint= 32_t val) break; } set_float_rounding_mode(i, &env->vfp.fp_status); + set_float_rounding_mode(i, &env->vfp.fp_status_f16); } - if (changed & (1 << 24)) { - set_flush_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_status); - set_flush_inputs_to_zero((val & (1 << 24)) !=3D 0, &env->vfp.fp_st= atus); + if (changed & FPCR_FZ16) { + bool ftz_enabled =3D val & FPCR_FZ16; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + } + if (changed & FPCR_FZ) { + bool ftz_enabled =3D val & FPCR_FZ; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); + } + if (changed & FPCR_DN) { + bool dnan_enabled =3D val & FPCR_DN; + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); } - if (changed & (1 << 25)) - set_default_nan_mode((val & (1 << 25)) !=3D 0, &env->vfp.fp_status= ); =20 + /* The exception flags are ORed together when we read fpscr so we + * only need to preserve the current state in one of our + * float_status values. + */ i =3D vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1c88539d62..2c64d2b3fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -637,16 +637,21 @@ static void write_fp_sreg(DisasContext *s, int reg, T= CGv_i32 v) tcg_temp_free_i64(tmp); } =20 -static TCGv_ptr get_fpstatus_ptr(void) +static TCGv_ptr get_fpstatus_ptr(bool is_f16) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); int offset; =20 - /* In A64 all instructions (both FP and Neon) use the FPCR; - * there is no equivalent of the A32 Neon "standard FPSCR value" - * and all operations use vfp.fp_status. + /* In A64 all instructions (both FP and Neon) use the FPCR; there + * is no equivalent of the A32 Neon "standard FPSCR value". + * However half-precision operations operate under a different + * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. */ - offset =3D offsetof(CPUARMState, vfp.fp_status); + if (is_f16) { + offset =3D offsetof(CPUARMState, vfp.fp_status_f16); + } else { + offset =3D offsetof(CPUARMState, vfp.fp_status); + } tcg_gen_addi_ptr(statusptr, cpu_env, offset); return statusptr; } @@ -4423,7 +4428,7 @@ static void handle_fp_compare(DisasContext *s, bool i= s_double, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_vn, tcg_vm; @@ -4598,7 +4603,7 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) TCGv_i32 tcg_op; TCGv_i32 tcg_res; =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_sreg(s, rn); tcg_res =3D tcg_temp_new_i32(); =20 @@ -4660,7 +4665,7 @@ static void handle_fp_1src_double(DisasContext *s, in= t opcode, int rd, int rn) return; } =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op =3D read_fp_dreg(s, rn); tcg_res =3D tcg_temp_new_i64(); =20 @@ -4840,7 +4845,7 @@ static void handle_fp_2src_single(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i32(); - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); =20 @@ -4893,7 +4898,7 @@ static void handle_fp_2src_double(DisasContext *s, in= t opcode, TCGv_ptr fpst; =20 tcg_res =3D tcg_temp_new_i64(); - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); =20 @@ -4979,7 +4984,7 @@ static void handle_fp_3src_single(DisasContext *s, bo= ol o0, bool o1, { TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 tcg_op1 =3D read_fp_sreg(s, rn); tcg_op2 =3D read_fp_sreg(s, rm); @@ -5017,7 +5022,7 @@ static void handle_fp_3src_double(DisasContext *s, bo= ol o0, bool o1, { TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 tcg_op1 =3D read_fp_dreg(s, rn); tcg_op2 =3D read_fp_dreg(s, rm); @@ -5158,7 +5163,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift; =20 - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); =20 tcg_shift =3D tcg_const_i32(64 - scale); =20 @@ -5870,7 +5875,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) TCGv_i32 tcg_elt1 =3D tcg_temp_new_i32(); TCGv_i32 tcg_elt2 =3D tcg_temp_new_i32(); TCGv_i32 tcg_elt3 =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 assert(esize =3D=3D 32); assert(elements =3D=3D 4); @@ -6372,7 +6377,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) } =20 size =3D extract32(size, 0, 1) ? 3 : 2; - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); break; default: unallocated_encoding(s); @@ -6864,7 +6869,7 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, int fracbits, int size) { bool is_double =3D size =3D=3D 3 ? true : false; - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); TCGv_i32 tcg_shift =3D tcg_const_i32(fracbits); TCGv_i64 tcg_int =3D tcg_temp_new_i64(); TCGMemOp mop =3D size | (is_signed ? MO_SIGN : 0); @@ -6980,7 +6985,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); tcg_shift =3D tcg_const_i32(fracbits); =20 if (is_double) { @@ -7326,7 +7331,7 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, int fpopcode, int rd, int rn, int rm) { int pass; - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 for (pass =3D 0; pass < elements; pass++) { if (size) { @@ -7790,7 +7795,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, return; } =20 - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -7897,7 +7902,7 @@ static void handle_2misc_reciprocal(DisasContext *s, = int opcode, int size, int rn, int rd) { bool is_double =3D (size =3D=3D 3); - TCGv_ptr fpst =3D get_fpstatus_ptr(); + TCGv_ptr fpst =3D get_fpstatus_ptr(false); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -8296,7 +8301,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_rmode =3D NULL; tcg_fpstatus =3D NULL; @@ -9516,7 +9521,7 @@ static void handle_simd_3same_pair(DisasContext *s, i= nt is_q, int u, int opcode, =20 /* Floating point operations need fpst */ if (opcode >=3D 0x58) { - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); } else { fpst =3D NULL; } @@ -10676,7 +10681,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) } =20 if (need_fpstatus) { - tcg_fpstatus =3D get_fpstatus_ptr(); + tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_fpstatus =3D NULL; } @@ -11056,7 +11061,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 if (is_fp) { - fpst =3D get_fpstatus_ptr(); + fpst =3D get_fpstatus_ptr(false); } else { fpst =3D NULL; } --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400679064578.6109647634751; Fri, 23 Feb 2018 07:44:39 -0800 (PST) Received: from localhost ([::1]:45278 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFWW-0001Rc-3s for importer@patchew.org; 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Fri, 23 Feb 2018 07:36:44 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:10 +0000 Message-Id: <20180223153636.29809-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 05/31] target/arm/helper: pass explicit fpst to set_rmode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++-- target/arm/helper.h | 2 +- target/arm/translate-a64.c | 26 +++++++++++++------------- target/arm/translate.c | 12 ++++++------ 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f450eb200f..303cd1eaf9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11393,9 +11393,9 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ -uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) +uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) { - float_status *fp_status =3D &env->vfp.fp_status; + float_status *fp_status =3D fpstp; =20 uint32_t prev_rmode =3D get_float_rounding_mode(fp_status); set_float_rounding_mode(rmode, fp_status); diff --git a/target/arm/helper.h b/target/arm/helper.h index 6383d7d09e..81ecb319b3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -167,7 +167,7 @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) =20 -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env) +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) =20 DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2c64d2b3fe..91c2b8ed11 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4628,10 +4628,10 @@ static void handle_fp_1src_single(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -4687,10 +4687,10 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) { TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tcg_res, tcg_op, fpst); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -5217,7 +5217,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); =20 if (is_double) { TCGv_i64 tcg_double =3D read_fp_dreg(s, rn); @@ -5264,7 +5264,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); =20 if (!sf) { @@ -6984,8 +6984,8 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, assert(!(is_scalar && is_q)); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_shift =3D tcg_const_i32(fracbits); =20 if (is_double) { @@ -7029,7 +7029,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, =20 tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_shift); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } =20 @@ -8300,8 +8300,8 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) =20 if (is_fcvt) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus =3D get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; tcg_fpstatus =3D NULL; @@ -8366,7 +8366,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) } =20 if (is_fcvt) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(tcg_fpstatus); } @@ -10680,14 +10680,14 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) return; } =20 - if (need_fpstatus) { + if (need_fpstatus || need_rmode) { tcg_fpstatus =3D get_fpstatus_ptr(false); } else { tcg_fpstatus =3D NULL; } if (need_rmode) { tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode =3D NULL; } @@ -10929,7 +10929,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) clear_vec_high(s, is_q, rd); =20 if (need_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } if (need_fpstatus) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 1270022289..aa6dcaa577 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3143,7 +3143,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, TCGv_i32 tcg_rmode; =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_op; @@ -3167,7 +3167,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, u= int32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_res); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_ptr(fpst); @@ -3184,7 +3184,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_shift =3D tcg_const_i32(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); =20 if (dp) { TCGv_i64 tcg_double, tcg_res; @@ -3222,7 +3222,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, ui= nt32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_single); } =20 - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 tcg_temp_free_i32(tcg_shift); @@ -3892,13 +3892,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) TCGv_ptr fpst =3D get_fpstatus_ptr(0); TCGv_i32 tcg_rmode; tcg_rmode =3D tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); } else { gen_helper_rints(cpu_F0s, cpu_F0s, fpst); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env= ); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(fpst); break; --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400506552998.5666782179516; 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Fri, 23 Feb 2018 07:36:43 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:11 +0000 Message-Id: <20180223153636.29809-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 06/31] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson -- v1 - dropped the advsimd_2a stuff v2 - fixed up checkpatch v3 - add TCG_CALL_NO_RWG to helper definitions --- target/arm/helper-a64.c | 18 ++++++ target/arm/helper-a64.h | 4 ++ target/arm/translate-a64.c | 142 ++++++++++++++++++++++++++++-------------= ---- 3 files changed, 110 insertions(+), 54 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 10e08bdc1f..fddd5d242b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -572,3 +572,21 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSt= ate *env, uint64_t addr, { return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()= ); } + +/* + * AdvSIMD half-precision + */ + +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suf= fix)) + +#define ADVSIMD_HALFOP(name) \ +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ +{ \ + float_status *fpst =3D fpstp; \ + return float16_ ## name(a, b, fpst); \ +} + +ADVSIMD_HALFOP(min) +ADVSIMD_HALFOP(max) +ADVSIMD_HALFOP(minnum) +ADVSIMD_HALFOP(maxnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 85d86741db..cb2a73124d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -48,3 +48,7 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL= _NO_WG, DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 91c2b8ed11..ebaf4571ac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5741,26 +5741,75 @@ static void disas_simd_zip_trn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i64(tcg_resh); } =20 -static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_e= lt2, - int opc, bool is_min, TCGv_ptr fpst) -{ - /* Helper function for disas_simd_across_lanes: do a single precision - * min/max operation on the specified two inputs, - * and return the result in tcg_elt1. - */ - if (opc =3D=3D 0xc) { - if (is_min) { - gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } +/* + * do_reduction_op helper + * + * This mirrors the Reduce() pseudocode in the ARM ARM. It is + * important for correct NaN propagation that we do these + * operations in exactly the order specified by the pseudocode. + * + * This is a recursive function, TCG temps should be freed by the + * calling function once it is done with the values. + */ +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, + int esize, int size, int vmap, TCGv_ptr fp= st) +{ + if (esize =3D=3D size) { + int element; + TCGMemOp msize =3D esize =3D=3D 16 ? MO_16 : MO_32; + TCGv_i32 tcg_elem; + + /* We should have one register left here */ + assert(ctpop8(vmap) =3D=3D 1); + element =3D ctz32(vmap); + assert(element < 8); + + tcg_elem =3D tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, element, msize); + return tcg_elem; } else { - assert(opc =3D=3D 0xf); - if (is_min) { - gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); + int bits =3D size / 2; + int shift =3D ctpop8(vmap) / 2; + int vmap_lo =3D (vmap >> shift) & vmap; + int vmap_hi =3D (vmap & ~vmap_lo); + TCGv_i32 tcg_hi, tcg_lo, tcg_res; + + tcg_hi =3D do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, = fpst); + tcg_lo =3D do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, = fpst); + tcg_res =3D tcg_temp_new_i32(); + + switch (fpopcode) { + case 0x0c: /* fmaxnmv half-precision */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x0f: /* fmaxv half-precision */ + gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1c: /* fminnmv half-precision */ + gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1f: /* fminv half-precision */ + gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2c: /* fmaxnmv */ + gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2f: /* fmaxv */ + gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3c: /* fminnmv */ + gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3f: /* fminv */ + gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); + break; + default: + g_assert_not_reached(); } + + tcg_temp_free_i32(tcg_hi); + tcg_temp_free_i32(tcg_lo); + return tcg_res; } } =20 @@ -5802,16 +5851,21 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) break; case 0xc: /* FMAXNMV, FMINNMV */ case 0xf: /* FMAXV, FMINV */ - if (!is_u || !is_q || extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - /* Bit 1 of size field encodes min vs max, and actual size is alwa= ys - * 32 bits: adjust the size variable so following code can rely on= it + /* Bit 1 of size field encodes min vs max and the actual size + * depends on the encoding of the U bit. If not set (and FP16 + * enabled) then we do half-precision float instead of single + * precision. */ is_min =3D extract32(size, 1, 1); is_fp =3D true; - size =3D 2; + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + size =3D 1; + } else if (!is_u || !is_q || extract32(size, 0, 1)) { + unallocated_encoding(s); + return; + } else { + size =3D 2; + } break; default: unallocated_encoding(s); @@ -5868,38 +5922,18 @@ static void disas_simd_across_lanes(DisasContext *s= , uint32_t insn) =20 } } else { - /* Floating point ops which work on 32 bit (single) intermediates. + /* Floating point vector reduction ops which work across 32 + * bit (single) or 16 bit (half-precision) intermediates. * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_i32 tcg_elt1 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_elt2 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_elt3 =3D tcg_temp_new_i32(); - TCGv_ptr fpst =3D get_fpstatus_ptr(false); - - assert(esize =3D=3D 32); - assert(elements =3D=3D 4); - - read_vec_element(s, tcg_elt, rn, 0, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt); - read_vec_element(s, tcg_elt, rn, 1, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - read_vec_element(s, tcg_elt, rn, 2, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - read_vec_element(s, tcg_elt, rn, 3, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt); - - do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); - tcg_temp_free_i32(tcg_elt1); - tcg_temp_free_i32(tcg_elt2); - tcg_temp_free_i32(tcg_elt3); + TCGv_ptr fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + int fpopcode =3D opcode | is_min << 4 | is_u << 5; + int vmap =3D (1 << elements) - 1; + TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, esize, + (is_q ? 128 : 64), vmap, fpst= ); + tcg_gen_extu_i32_i64(tcg_res, tcg_res32); + tcg_temp_free_i32(tcg_res32); tcg_temp_free_ptr(fpst); } =20 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400343165119.8607492009047; Fri, 23 Feb 2018 07:39:03 -0800 (PST) Received: from localhost ([::1]:45239 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFR8-0004LI-9g for importer@patchew.org; Fri, 23 Feb 2018 10:39:02 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFOx-0002mO-I9 for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFOw-00077J-NJ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:47 -0500 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:37265) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFOw-00075J-FR for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:46 -0500 Received: by mail-wr0-x242.google.com with SMTP id z12so14530346wrg.4 for ; Fri, 23 Feb 2018 07:36:46 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 72sm2009208wmh.44.2018.02.23.07.36.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 0B7C33E047D; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Iw0vC7G/Fdearlly0m3YmrmwA6Bs9KCNgEwTL/OBByU=; b=Gw6Rec5rOMUCMCWbrSRWuWk0yKALSqwB8XZsccHMBoaBo2WSKXqsby+4Uo8GD5cHQu Mk0/sgrOaOXGDBlqGptmGfntdf2yGYtSF/+QuspI7Qam/VhkBxDqczsH0jQcrT6nj37i aLZ3O85csTY4tPPnI4DelpU07NN3ye+3Y0yP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Iw0vC7G/Fdearlly0m3YmrmwA6Bs9KCNgEwTL/OBByU=; b=KJV0gHwbwXmNInCB9fO/db/lBaWj3wFK+1RqSnxFX9LHCeKrqkph+8jbKRPvdhYleb JPCjYPCBMO4qolniv5TqfvjNIJaitHAUlwrXoEmp9/0fPToDTWs5d1JIPr5MX0W+R6kx 4FN1G6Gj4r/jWcIKVSt8Nijkvcji5izeowEHIDHKg7CPN1JioK+fp7U3Z4kHbrbt5rZi QHs2P8QE5pMAVndRv6c/L+1YIsSIFwg+3SSeU5V544hussABrdAk4k1de0p4KLfBnXWt m83UpvrbUN04j2tyAcjhHRhyeCIDKtspnG7AQzS1TII2cXBDGESRFcDgNyFzQYa3qUXs mOjg== X-Gm-Message-State: APf1xPDu+gM3r2rDrPwbc7kz5FRuRAtE0kn0jCVbhY6L0Ae4z0QFoHLF rNGZbwU3zROY5nlT5fi5w+4UGA== X-Google-Smtp-Source: AH8x224vjjUUFnZ0sMpZ5MADjuwe0MQZH+FBVpJVKMCZVDpwgKQHwm9O1aTweD8b1V/XT+HwyT/uXA== X-Received: by 10.223.152.228 with SMTP id w91mr1919729wrb.74.1519400205415; Fri, 23 Feb 2018 07:36:45 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:12 +0000 Message-Id: <20180223153636.29809-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 07/31] arm/translate-a64: handle_3same_64 comment fix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We do implement all the opcodes. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ebaf4571ac..5dd54b7ac4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7278,8 +7278,7 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, /* Handle 64x64->64 opcodes which are shared between the scalar * and vector 3-same groups. We cover every opcode where size =3D=3D 3 * is valid in either the three-reg-same (integer, not pairwise) - * or scalar-three-reg-same groups. (Some opcodes are not yet - * implemented.) + * or scalar-three-reg-same groups. */ TCGCond cond; =20 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400671416589.4515835280727; Fri, 23 Feb 2018 07:44:31 -0800 (PST) Received: from localhost ([::1]:45277 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFWQ-0001Fs-Fi for importer@patchew.org; Fri, 23 Feb 2018 10:44:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFOz-0002oB-1E for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFOx-0007A6-TR for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:49 -0500 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:36510) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFOx-00078B-LQ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:47 -0500 Received: by mail-wr0-x243.google.com with SMTP id v111so2300746wrb.3 for ; Fri, 23 Feb 2018 07:36:47 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id w31sm3715921wrc.49.2018.02.23.07.36.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:42 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 1D1DB3E055F; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5e92OlfPhH3uuKn8l58mdAFexdWXszJjfX8UyDvWKY8=; b=N7P/6L3ZiOMtrUsFsO2iJaBM1EA+7WOc5XEnm6Tyc3Ch5cjx/jkf2Q/KTzrV4sqTd/ RewVzodMrXVzbniCnsBp4xUSe96ub0SxcpEksunTKWoSiY9pnL6cxsYgaRIe/toIkXaK nzy+jkhk7DHLfDTEkV6ZlwjutzDLkmak2tx5c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5e92OlfPhH3uuKn8l58mdAFexdWXszJjfX8UyDvWKY8=; b=WH4UXPTKCt4VVqSHlSwxKRUCJm0QgYycPLNltJt4dkhZCVI/Pmm+V79FPQs+glh6Q6 irkCOrLshkSdK25iE5A/Y3FFrOibBvAMQ1nozLiJgnAQAVmo8SqwZrqzxfu+CJ9btOx/ 6dnwo4HBiYzOKE9ZXboBHlmUqbTum4hEE83XxcQRVY62l8w7bVdJ4Sw8JDFLRx9jc7Tn aJi3wHv93dtXZ+Ajh3iuk/PBtelRgHeM6KYwgNclvI3c6oZpQPQ0wh3GKQ4mhGqohCHH 0LW6KcKm3Wc5NJrvLJLuAwskGgiWcR2bEeEyz7Vo2E8bYUtvvQgE0mQ9ewpqe9rGu0jA kyDw== X-Gm-Message-State: APf1xPDtkTuNxXiBRHpzn1tJV3GRVS1Pw32HCeAMaMx25rwslZRDvO43 xw0LSPkqOi+VUoH7mLT/v+e3qA== X-Google-Smtp-Source: AH8x226HrISEfDjGrT0RNuXQSYxh5/d9t1xbCVNfxhI+uuSIbRZZ0g/qML/KpKrruv1/xRhqDR5CsA== X-Received: by 10.223.178.232 with SMTP id g95mr2188451wrd.35.1519400206541; Fri, 23 Feb 2018 07:36:46 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:13 +0000 Message-Id: <20180223153636.29809-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v3 08/31] arm/translate-a64: initial decode for simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 73 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5dd54b7ac4..4828457b5b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10228,6 +10228,78 @@ static void disas_simd_three_reg_same(DisasContext= *s, uint32_t insn) } } =20 +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 = 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | R= d | + * +---+---+---+-----------+---------+------+-----+--------+---+------+---= ---+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode =3D extract32(insn, 11, 3); + u =3D extract32(insn, 29, 1); + a =3D extract32(insn, 23, 1); + is_q =3D extract32(insn, 30, 1); + rm =3D extract32(insn, 16, 5); + rn =3D extract32(insn, 5, 5); + rd =3D extract32(insn, 0, 5); + + fpopcode =3D opcode | (a << 3) | (u << 4); + datasize =3D is_q ? 128 : 64; + elements =3D datasize / 16; + + fpst =3D get_fpstatus_ptr(true); + + for (pass =3D 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + clear_vec_high(s, is_q, rd); +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11975,6 +12047,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce000000, 0xff808000, disas_crypto_four_reg }, { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 09/31] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - add absh helper - fix checkpatch violation - make abs a bitwise operation --- target/arm/helper-a64.c | 4 ++++ target/arm/helper-a64.h | 4 ++++ target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index fddd5d242b..931a6d3c34 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -586,6 +586,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, = void *fpstp) \ return float16_ ## name(a, b, fpst); \ } =20 +ADVSIMD_HALFOP(add) +ADVSIMD_HALFOP(sub) +ADVSIMD_HALFOP(mul) +ADVSIMD_HALFOP(div) ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index cb2a73124d..bac9469426 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -52,3 +52,7 @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f1= 6, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4828457b5b..f8770ee1e9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10283,6 +10283,34 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); =20 switch (fpopcode) { + case 0x0: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xa: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xe: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x13: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x17: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 10/31] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/helper-a64.h | 5 +++++ target/arm/translate-a64.c | 15 ++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 931a6d3c34..d0b284fec4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -594,3 +594,52 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* + * Floating point comparisons produce an integer result. Softfloat + * routines return float_relation types which we convert to the 0/-1 + * Neon requires. + */ + +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 + +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare_quiet(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + int compare =3D float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal); +} + +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f0 =3D float16_abs(a); + float16 f1 =3D float16_abs(b); + int compare =3D float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index bac9469426..1cf40bda5e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -56,3 +56,8 @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f8770ee1e9..fb74dc1c45 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10289,6 +10289,9 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10304,6 +10307,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x17: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10311,6 +10320,12 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151940083131868.59824161006202; Fri, 23 Feb 2018 07:47:11 -0800 (PST) Received: from localhost ([::1]:45303 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFZ0-0003uR-7f for importer@patchew.org; Fri, 23 Feb 2018 10:47:10 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFUh-0008Qi-1E for qemu-devel@nongnu.org; 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Fri, 23 Feb 2018 07:42:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:16 +0000 Message-Id: <20180223153636.29809-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 11/31] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 24 ++++++++++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 15 +++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d0b284fec4..1ef13abd76 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -595,6 +595,30 @@ ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) =20 +/* Data processing - scalar floating-point and advanced SIMD */ +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + + a =3D float16_squash_input_denormal(a, fpst); + b =3D float16_squash_input_denormal(b, fpst); + + if ((float16_is_zero(a) && float16_is_infinity(b)) || + (float16_is_infinity(a) && float16_is_zero(b))) { + /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ + return make_float16((1U << 14) | + ((float16_val(a) ^ float16_val(b)) & (1U << 15= ))); + } + return float16_mul(a, b, fpst); +} + +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fps= tp) +{ + float_status *fpst =3D fpstp; + return float16_muladd(a, b, c, 0, fpst); +} + /* * Floating point comparisons produce an integer result. Softfloat * routines return float_relation types which we convert to the 0/-1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 1cf40bda5e..9c1a95594c 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -61,3 +61,5 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fb74dc1c45..0e2d298687 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10286,9 +10286,17 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) case 0x0: /* FMAXNM */ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x1: /* FMLA */ + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x3: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x4: /* FCMEQ */ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10298,6 +10306,13 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) case 0x8: /* FMINNM */ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x9: /* FMLS */ + /* As usual for ARM, separate negation for fused multiply-add= */ + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0xa: /* FSUB */ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); break; --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 12/31] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Aurelien Jarno , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 As some of the constants here will also be needed elsewhere (specifically for the upcoming SVE support) we move them out to softfloat.h. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - move constants used for estimate to softfloat.h --- include/fpu/softfloat.h | 16 ++++++++++++---- target/arm/helper-a64.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 6 ++++++ 4 files changed, 54 insertions(+), 4 deletions(-) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 9b7b5e34e2..27876e711c 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -306,8 +306,11 @@ static inline float16 float16_set_sign(float16 a, int = sign) } =20 #define float16_zero make_float16(0) -#define float16_one make_float16(0x3c00) #define float16_half make_float16(0x3800) +#define float16_one make_float16(0x3c00) +#define float16_one_point_five make_float16(0x3e00) +#define float16_two make_float16(0x4000) +#define float16_three make_float16(0x4200) #define float16_infinity make_float16(0x7c00) =20 /*------------------------------------------------------------------------= ---- @@ -415,11 +418,13 @@ static inline float32 float32_set_sign(float32 a, int= sign) } =20 #define float32_zero make_float32(0) -#define float32_one make_float32(0x3f800000) #define float32_half make_float32(0x3f000000) +#define float32_one make_float32(0x3f800000) +#define float32_one_point_five make_float32(0x3fc00000) +#define float32_two make_float32(0x40000000) +#define float32_three make_float32(0x40400000) #define float32_infinity make_float32(0x7f800000) =20 - /*------------------------------------------------------------------------= ---- | The pattern for a default generated single-precision NaN. *-------------------------------------------------------------------------= ---*/ @@ -526,9 +531,12 @@ static inline float64 float64_set_sign(float64 a, int = sign) } =20 #define float64_zero make_float64(0) +#define float64_half make_float64(0x3fe0000000000000LL) #define float64_one make_float64(0x3ff0000000000000LL) +#define float64_one_point_five make_float64(0x3FF8000000000000ULL) +#define float64_two make_float64(0x4000000000000000ULL) +#define float64_three make_float64(0x4008000000000000ULL) #define float64_ln2 make_float64(0x3fe62e42fefa39efLL) -#define float64_half make_float64(0x3fe0000000000000LL) #define float64_infinity make_float64(0x7ff0000000000000LL) =20 /*------------------------------------------------------------------------= ---- diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 1ef13abd76..8fdbe034f3 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -192,6 +192,10 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, vo= id *fpstp) * versions, these do a fully fused multiply-add or * multiply-add-and-halve. */ +#define float16_two make_float16(0x4000) +#define float16_three make_float16(0x4200) +#define float16_one_point_five make_float16(0x3e00) + #define float32_two make_float32(0x40000000) #define float32_three make_float32(0x40400000) #define float32_one_point_five make_float32(0x3fc00000) @@ -200,6 +204,21 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, vo= id *fpstp) #define float64_three make_float64(0x4008000000000000ULL) #define float64_one_point_five make_float64(0x3FF8000000000000ULL) =20 +float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + + a =3D float16_squash_input_denormal(a, fpst); + b =3D float16_squash_input_denormal(b, fpst); + + a =3D float16_chs(a); + if ((float16_is_infinity(a) && float16_is_zero(b)) || + (float16_is_infinity(b) && float16_is_zero(a))) { + return float16_two; + } + return float16_muladd(a, b, float16_two, 0, fpst); +} + float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp) { float_status *fpst =3D fpstp; @@ -230,6 +249,21 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void = *fpstp) return float64_muladd(a, b, float64_two, 0, fpst); } =20 +float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + + a =3D float16_squash_input_denormal(a, fpst); + b =3D float16_squash_input_denormal(b, fpst); + + a =3D float16_chs(a); + if ((float16_is_infinity(a) && float16_is_zero(b)) || + (float16_is_infinity(b) && float16_is_zero(a))) { + return float16_one_point_five; + } + return float16_muladd(a, b, float16_three, float_muladd_halve_result, = fpst); +} + float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp) { float_status *fpst =3D fpstp; diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 9c1a95594c..79012eee9d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -29,8 +29,10 @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64,= f64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) +DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) +DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0e2d298687..217e73ef58 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10303,6 +10303,9 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x7: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x8: /* FMINNM */ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10319,6 +10322,9 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) case 0xe: /* FMIN */ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0xf: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v3 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++------------= ---- 1 file changed, 133 insertions(+), 75 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 217e73ef58..e96e6cdd15 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10247,6 +10247,7 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) int datasize, elements; int pass; TCGv_ptr fpst; + bool pairwise =3D false; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); @@ -10272,91 +10273,148 @@ static void disas_simd_three_reg_same_fp16(Disas= Context *s, uint32_t insn) datasize =3D is_q ? 128 : 64; elements =3D datasize / 16; =20 + switch (fpopcode) { + case 0x10: /* FMAXNMP */ + case 0x12: /* FADDP */ + case 0x16: /* FMAXP */ + case 0x18: /* FMINNMP */ + case 0x1e: /* FMINP */ + pairwise =3D true; + break; + } + fpst =3D get_fpstatus_ptr(true); =20 - for (pass =3D 0; pass < elements; pass++) { + if (pairwise) { + int maxpass =3D is_q ? 8 : 4; TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res[8]; =20 - read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); - read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + for (pass =3D 0; pass < maxpass; pass++) { + int passreg =3D pass < (maxpass / 2) ? rn : rm; + int passelt =3D (pass << 1) & (maxpass - 1); =20 - switch (fpopcode) { - case 0x0: /* FMAXNM */ - gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_16); - gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, - fpst); - break; - case 0x2: /* FADD */ - gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x3: /* FMULX */ - gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x4: /* FCMEQ */ - gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x6: /* FMAX */ - gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x7: /* FRECPS */ - gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x8: /* FMINNM */ - gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x9: /* FMLS */ - /* As usual for ARM, separate negation for fused multiply-add= */ - tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); - read_vec_element_i32(s, tcg_res, rd, pass, MO_16); - gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, - fpst); - break; - case 0xa: /* FSUB */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xe: /* FMIN */ - gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xf: /* FRSQRTS */ - gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x13: /* FMUL */ - gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x14: /* FCMGE */ - gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x15: /* FACGE */ - gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x17: /* FDIV */ - gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1a: /* FABD */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); - break; - case 0x1c: /* FCMGT */ - gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1d: /* FACGT */ - gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - default: - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", - __func__, insn, fpopcode, s->pc); - g_assert_not_reached(); + read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); + read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); + tcg_res[pass] =3D tcg_temp_new_i32(); + + switch (fpopcode) { + case 0x10: /* FMAXNMP */ + gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, + fpst); + break; + case 0x12: /* FADDP */ + gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, f= pst); + break; + case 0x16: /* FMAXP */ + gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, f= pst); + break; + case 0x18: /* FMINNMP */ + gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, + fpst); + break; + case 0x1e: /* FMINP */ + gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, f= pst); + break; + default: + g_assert_not_reached(); + } + } + + for (pass =3D 0; pass < maxpass; pass++) { + write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); + tcg_temp_free_i32(tcg_res[pass]); } =20 - write_vec_element_i32(s, tcg_res, rd, pass, MO_16); - tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_op1); tcg_temp_free_i32(tcg_op2); + + } else { + for (pass =3D 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + case 0x0: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x1: /* FMLA */ + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_= res, + fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x3: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x7: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x9: /* FMLS */ + /* As usual for ARM, separate negation for fused multiply-= add */ + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_= res, + fpst); + break; + case 0xa: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xe: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x13: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fps= t); + break; + case 0x17: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); + break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fps= t); + break; + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\= n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } } =20 tcg_temp_free_ptr(fpst); --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401467715851.2889248239408; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v3 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The helpers use the new re-factored muladd support in SoftFloat for the float16 work. Signed-off-by: Alex Benn=C3=A9e --- v3 - re-jigged switch statement to fall-through for unalloc - added is_fp16 bool for fpst - fixed up some long lines --- target/arm/translate-a64.c | 83 +++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 67 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e96e6cdd15..43bff5cd09 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11198,6 +11198,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) int rd =3D extract32(insn, 0, 5); bool is_long =3D false; bool is_fp =3D false; + bool is_fp16 =3D false; int index; TCGv_ptr fpst; =20 @@ -11244,7 +11245,8 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } /* fall through */ case 0x9: /* FMUL, FMULX */ - if (!extract32(size, 1, 1)) { + if (size =3D=3D 1 || + (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { unallocated_encoding(s); return; } @@ -11256,18 +11258,34 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) } =20 if (is_fp) { - /* low bit of size indicates single/double */ - size =3D extract32(size, 0, 1) ? 3 : 2; - if (size =3D=3D 2) { + /* convert insn encoded size to TCGMemOp size */ + switch (size) { + case 2: /* single precision */ + size =3D MO_32; index =3D h << 1 | l; - } else { + rm |=3D (m << 4); + break; + case 3: /* double precision */ + size =3D MO_64; if (l || !is_q) { unallocated_encoding(s); return; } index =3D h; + rm |=3D (m << 4); + break; + case 0: /* half precision */ + size =3D MO_16; + index =3D h << 2 | l << 1 | m; + is_fp16 =3D true; + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ + default: /* unallocated */ + unallocated_encoding(s); + return; } - rm |=3D (m << 4); } else { switch (size) { case 1: @@ -11288,7 +11306,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 if (is_fp) { - fpst =3D get_fpstatus_ptr(false); + fpst =3D get_fpstatus_ptr(is_fp16); } else { fpst =3D NULL; } @@ -11390,18 +11408,51 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) break; } case 0x5: /* FMLS */ - /* As usual for ARM, separate negation for fused multiply-= add */ - gen_helper_vfp_negs(tcg_op, tcg_op); - /* fall through */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_32); - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, = fpst); + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + switch (size) { + case 1: + if (opcode =3D=3D 0x5) { + /* As usual for ARM, separate negation for fused + * multiply-add */ + tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); + } + gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, + tcg_res, fpst); + break; + case 2: + if (opcode =3D=3D 0x5) { + /* As usual for ARM, separate negation for + * fused multiply-add */ + tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); + } + gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, + tcg_res, fpst); + break; + default: + g_assert_not_reached(); + } break; case 0x9: /* FMUL, FMULX */ - if (u) { - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + switch (size) { + case 1: + if (u) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, + fpst); + } else { + g_assert_not_reached(); + } + break; + case 2: + if (u) { + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fps= t); + } else { + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst= ); + } + break; + default: + g_assert_not_reached(); } break; case 0xc: /* SQDMULH */ --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401088020465.27625963714627; Fri, 23 Feb 2018 07:51:28 -0800 (PST) Received: from localhost ([::1]:45329 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFd9-0007l7-0Q for importer@patchew.org; Fri, 23 Feb 2018 10:51:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45933) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFUh-0008Qt-3U for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFUd-0005by-JQ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:43 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:53242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFUd-0005Zu-8k for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:39 -0500 Received: by mail-wm0-x242.google.com with SMTP id t3so5438512wmc.2 for ; Fri, 23 Feb 2018 07:42:39 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id i33sm2673188wri.70.2018.02.23.07.42.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:42:32 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A44553E0BDF; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WJduKqLIuBTHq6WFzmTmo4jkE6BcZz/VbT4+ImZgbsk=; b=EOqOaFURzsHG/KQw7Wyipgp82mnEW8qT627SEIvL1x1sPeHw06ytJ+IGZItx0MZerK +KdaRDbLQYwGR0Pcd4IE3nNSXx+xQkYt9jyKk+2f62YRrg37NsD87RCieY5+zM0CjyU3 wS8VXvAcEla2j1iFSI6TH8nU8LlhcwryfXdws= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WJduKqLIuBTHq6WFzmTmo4jkE6BcZz/VbT4+ImZgbsk=; b=cDZN7eXbuZfp0veGRRTz1i/xLHRYI8raixb98VAH4ATJQf6ILUCcdQtbukyumgnwfE +y8glJsuimqrE+KytzLb62L0ZpT6PFdmsjhET1TsALAYqpHdqInum1OmesQdCkooeK2y jCLDk2xji3y7q/CdvtGRMaP/Y9EEPl/vaBSQw6izNCkeC7Y7BlUUnydEQc1M8Bv77/os 1mdO3hHh//8AdfoRU8F4g4XJLZ4gPUM+nclcDC6Rk4Op1EVwvZMVe9eoS4cCA3E2BGl8 FmlrVyDxg4a3jv+aTjtFpoQtKIyu+XPzmkynE0iVgz1j63xxz4P3N09096+gu359jn+q bowQ== X-Gm-Message-State: APf1xPDpn0hG1fhxOZXBoMJLafgS9E8+869UFBiIaN3sJgPGmhLMAwYr V9aSaXqW+fJ7QFJ7oIXGEH0cpNlXJxg= X-Google-Smtp-Source: AG47ELtkKt5mYG4OMsR0C4Vf6G3m2jeiE+LauItYZemyeRgDvjbu0QXF4WIQqD++3Pomgk0huMu3Pg== X-Received: by 10.28.237.19 with SMTP id l19mr1965325wmh.157.1519400558133; Fri, 23 Feb 2018 07:42:38 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:20 +0000 Message-Id: <20180223153636.29809-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 15/31] arm/translate-a64: add FP16 x2 ops for simd_indexed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes --- target/arm/helper-a64.c | 46 ++++++++++++++++++++++++++++++++++++++++++= +++- target/arm/helper-a64.h | 10 ++++++++++ target/arm/translate-a64.c | 26 +++++++++++++++++++++----- 3 files changed, 76 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 8fdbe034f3..4d5ae96d8f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -629,8 +629,32 @@ ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) =20 +#define ADVSIMD_TWOHALFOP(name) \ +uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fp= stp) \ +{ \ + float16 a1, a2, b1, b2; \ + uint32_t r1, r2; \ + float_status *fpst =3D fpstp; \ + a1 =3D extract32(two_a, 0, 16); \ + a2 =3D extract32(two_a, 16, 16); \ + b1 =3D extract32(two_b, 0, 16); \ + b2 =3D extract32(two_b, 16, 16); \ + r1 =3D float16_ ## name(a1, b1, fpst); \ + r2 =3D float16_ ## name(a2, b2, fpst); \ + return deposit32(r1, 16, 16, r2); \ +} + +ADVSIMD_TWOHALFOP(add) +ADVSIMD_TWOHALFOP(sub) +ADVSIMD_TWOHALFOP(mul) +ADVSIMD_TWOHALFOP(div) +ADVSIMD_TWOHALFOP(min) +ADVSIMD_TWOHALFOP(max) +ADVSIMD_TWOHALFOP(minnum) +ADVSIMD_TWOHALFOP(maxnum) + /* Data processing - scalar floating-point and advanced SIMD */ -float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +static float16 float16_mulx(float16 a, float16 b, void *fpstp) { float_status *fpst =3D fpstp; =20 @@ -646,6 +670,9 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, voi= d *fpstp) return float16_mul(a, b, fpst); } =20 +ADVSIMD_HALFOP(mulx) +ADVSIMD_TWOHALFOP(mulx) + /* fused multiply-accumulate */ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fps= tp) { @@ -653,6 +680,23 @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, = float16 c, void *fpstp) return float16_muladd(a, b, c, 0, fpst); } =20 +uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b, + uint32_t two_c, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 a1, a2, b1, b2, c1, c2; + uint32_t r1, r2; + a1 =3D extract32(two_a, 0, 16); + a2 =3D extract32(two_a, 16, 16); + b1 =3D extract32(two_b, 0, 16); + b2 =3D extract32(two_b, 16, 16); + c1 =3D extract32(two_c, 0, 16); + c2 =3D extract32(two_c, 16, 16); + r1 =3D float16_muladd(a1, b1, c1, 0, fpst); + r2 =3D float16_muladd(a2, b2, c2, 0, fpst); + return deposit32(r1, 16, 16, r2); +} + /* * Floating point comparisons produce an integer result. Softfloat * routines return float_relation types which we convert to the 0/-1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 79012eee9d..003ffa582f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -65,3 +65,13 @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) +DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 43bff5cd09..081619a389 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11418,8 +11418,13 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) * multiply-add */ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); } - gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, - tcg_res, fpst); + if (is_scalar) { + gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_id= x, + tcg_res, fpst); + } else { + gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_i= dx, + tcg_res, fpst); + } break; case 2: if (opcode =3D=3D 0x5) { @@ -11438,10 +11443,21 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) switch (size) { case 1: if (u) { - gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, - fpst); + if (is_scalar) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, + tcg_idx, fpst); + } else { + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, + tcg_idx, fpst); + } } else { - g_assert_not_reached(); + if (is_scalar) { + gen_helper_advsimd_mulh(tcg_res, tcg_op, + tcg_idx, fpst); + } else { + gen_helper_advsimd_mul2h(tcg_res, tcg_op, + tcg_idx, fpst); + } } break; case 2: --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v3 16/31] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions are only available in the vector form. This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch cleanups v3 - update comment on group from following patches. - rm left over debug fpf --- target/arm/translate-a64.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 081619a389..ea453fb6d9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11164,6 +11164,45 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) } } =20 +/* AdvSIMD [scalar] two register miscellaneous (FP16) + * + * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 = 0 + * +---+---+---+---+---------+---+-------------+--------+-----+------+----= --+ + * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd= | + * +---+---+---+---+---------+---+-------------+--------+-----+------+----= --+ + * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 + * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 + * + * This actually covers two groups where scalar access is governed by + * bit 28. A bunch of the instructions (float to integral) only exist + * in the vector form and are un-allocated for the scalar decode. Also + * in the scalar decode Q is always 1. + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode =3D extract32(insn, 12, 4); + a =3D extract32(insn, 23, 1); + fpop =3D deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+-----= -+ @@ -12237,6 +12276,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce800000, 0xffe00000, disas_crypto_xar }, { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401020009575.1371403230119; Fri, 23 Feb 2018 07:50:20 -0800 (PST) Received: from localhost ([::1]:45321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFc3-0006jd-0k for importer@patchew.org; Fri, 23 Feb 2018 10:50:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44559) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFP6-0002x5-4Y for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFP4-0007UD-RW for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:56 -0500 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:39190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFP4-0007RD-Hq for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:54 -0500 Received: by mail-wm0-x241.google.com with SMTP id 191so5339413wmm.4 for ; Fri, 23 Feb 2018 07:36:54 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c56sm4608499wrc.82.2018.02.23.07.36.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:46 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id C9B6C3E0085; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GOuiGLXkDPfPGFB/vV/7m/UoQhAzDhiKAwdRzroXsIo=; b=fhwSh181OWDzIWhGRDS8uex+uP8P2M2Co8k4rNi/JLzqmtSi2MzG/oKJ5mAZ1kGmZb i3cTeUzoKX6stAPTC2e9PbZHpKY5Ngz9ab0BFiQrZP3CYbLSWa8wKKSDCT8el6CCs3r0 2GjgHobFcNHYQ8SD1ErvZBZ8yOGOpReMzxGLQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GOuiGLXkDPfPGFB/vV/7m/UoQhAzDhiKAwdRzroXsIo=; b=LMgJfcfeQG4a+AYLMUePVUAczj4hbJsoSjfLZKw8AKLzFp4ptrAdCXmWD3/kOnFKbV L/5hA5C4HaCO4bjoekg0+RFBWLOl0DlHYcvkU7I8y+hq4qLNfxt5eXCxPcNLfuKGDmPD 4Ra5FpdvSQMus6+Ue1EnHRSCLo5MwsqYb8AuupsLvCXRr9+t1w0wY3xsxl8kYq8ZzIQF 60wET0SpkjSD+uedIPy8JcyyXon9b8ZiG6Q9EiYnwBKrxmlMeph05hMBIkFF0c7EpO6t P7nk8NAwWd+WqtWpuj/iL/N2H/3FFsuoevlZAtMNEDS5KcB2ei9rlJ8Q/J41bW32JoRr IUQg== X-Gm-Message-State: APf1xPDy85xrWWlC1IRwvKaLvk3eEV4JUw8OxVpj8ebX4uuhlrLYJq16 mBF3w1OSiafC58+GWCc4qwLd7w== X-Google-Smtp-Source: AG47ELvcFEnYEmriIpOWZzQkzxdbzc8+2DG/8VNe603MKydcEJPimfAlYjXxvd3Wpn8H+KgTwpHx0w== X-Received: by 10.28.158.197 with SMTP id h188mr2194718wme.72.1519400213409; Fri, 23 Feb 2018 07:36:53 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:22 +0000 Message-Id: <20180223153636.29809-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 17/31] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - fix re-base conflicts - move comment to previous commit - don't double test is_scalar in unallocated checks --- target/arm/helper-a64.c | 22 ++++++++ target/arm/helper-a64.h | 2 + target/arm/translate-a64.c | 123 +++++++++++++++++++++++++++++++++++++++++= ++-- 3 files changed, 142 insertions(+), 5 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4d5ae96d8f..4fd28fdf48 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -745,3 +745,25 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b= , void *fpstp) int compare =3D float16_compare(f0, f1, fpst); return ADVSIMD_CMPRES(compare =3D=3D float_relation_greater); } + +/* round to integral */ +float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status) +{ + return float16_round_to_int(x, fp_status); +} + +float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) +{ + int old_flags =3D get_float_exception_flags(fp_status), new_flags; + float16 ret; + + ret =3D float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags =3D get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_stat= us); + } + + return ret; +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 003ffa582f..bc8d5b105b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -75,3 +75,5 @@ DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) +DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ea453fb6d9..6f33663c7b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11180,27 +11180,140 @@ static void disas_simd_two_reg_misc(DisasContext= *s, uint32_t insn) */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { - int fpop, opcode, a; + int fpop, opcode, a, u; + int rn, rd; + bool is_q; + bool is_scalar; + bool only_in_vector =3D false; + + int pass; + TCGv_i32 tcg_rmode =3D NULL; + TCGv_ptr tcg_fpstatus =3D NULL; + bool need_rmode =3D false; + int rmode; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } =20 - if (!fp_access_check(s)) { - return; - } + rd =3D extract32(insn, 0, 5); + rn =3D extract32(insn, 5, 5); =20 - opcode =3D extract32(insn, 12, 4); a =3D extract32(insn, 23, 1); + u =3D extract32(insn, 29, 1); + is_scalar =3D extract32(insn, 28, 1); + is_q =3D extract32(insn, 30, 1); + + opcode =3D extract32(insn, 12, 5); fpop =3D deposit32(opcode, 5, 1, a); + fpop =3D deposit32(fpop, 6, 1, u); =20 switch (fpop) { + case 0x18: /* FRINTN */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x19: /* FRINTM */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x38: /* FRINTP */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x39: /* FRINTZ */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_ZERO; + break; + case 0x58: /* FRINTA */ + need_rmode =3D true; + only_in_vector =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x59: /* FRINTX */ + case 0x79: /* FRINTI */ + only_in_vector =3D true; + /* current rounding mode */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); } =20 + + /* Check additional constraints for the scalar encoding */ + if (is_scalar) { + if (!is_q) { + unallocated_encoding(s); + return; + } + /* FRINTxx is only in the vector form */ + if (only_in_vector) { + unallocated_encoding(s); + return; + } + } + + if (!fp_access_check(s)) { + return; + } + + if (need_rmode) { + tcg_fpstatus =3D get_fpstatus_ptr(true); + } + + if (need_rmode) { + tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + } + + if (is_scalar) { + /* no operations yet */ + } else { + for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_16); + + switch (fpop) { + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + case 0x58: /* FRINTA */ + case 0x79: /* FRINTI */ + gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x59: /* FRINTX */ + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstat= us); + break; + default: + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + } + + clear_vec_high(s, is_q, rd); + } + + if (tcg_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_temp_free_i32(tcg_rmode); + } + + if (tcg_fpstatus) { + tcg_temp_free_ptr(tcg_fpstatus); + } } =20 /* AdvSIMD scalar x indexed element --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400842880230.61012183561218; Fri, 23 Feb 2018 07:47:22 -0800 (PST) Received: from localhost ([::1]:45304 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFZC-00044k-21 for importer@patchew.org; Fri, 23 Feb 2018 10:47:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44541) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFP5-0002vs-3Y for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFP3-0007QM-Kv for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:55 -0500 Received: from mail-wr0-x244.google.com ([2a00:1450:400c:c0c::244]:39676) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFP3-0007Ni-Bc for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:36:53 -0500 Received: by mail-wr0-x244.google.com with SMTP id w77so14496522wrc.6 for ; Fri, 23 Feb 2018 07:36:53 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id k2sm4986134wrc.30.2018.02.23.07.36.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:36:46 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id DE27F3E0C29; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=liruGczDscf+xwX8NQVPCNn322BdQEfwljw776ud/Y4=; b=Rc9FENPy39HkBHlzufqDO71iH1ytD9PV4bKa5jUmhzAWgIVYpJ8we4TJKeZaYedAJD +U37iNAqPNsvxZzURaKZr6l8eqODSkNN+3YQKMm9978q1wBMpZkbjAoGo26G0jhjcrf5 6asgfmmbGbwMPDWST7aCkW+HpCiMtqUdsy/vY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=liruGczDscf+xwX8NQVPCNn322BdQEfwljw776ud/Y4=; b=KChlyzKSqvm4aCxQHKnCk2r6cg5zJmIZpLxUIrihwxYcXCdWqmoSDv1BUrmklDZ+u9 8bwEtvozq+ptRC4K7kzk5hF3DyKt/AehNxypoE2/hQKWjh2Jh17zVKrI0B71XmZW2dX1 ITfwkBde/ARQzPN1oPkexlaYSlgZASeztrwTAvuKGuXv3k/tBxw47riiRBkeD79dEPf+ wVTqsCijjbmyFCuWcwNHchfmI7mOzvRgGCY9RreOp7pIR1q2VTWkyR/ABPLa1ZojAm+k dL4Sk9HTWKVITs6OE6ILwW8OmDFcfP8Z7xJsBnq2X2aDLUOu7Ns63WVO3ZaNyk+W20CZ XFMg== X-Gm-Message-State: APf1xPCj9UjmPcqi9DlSqf4G3X9HA1J68bk/qCoKhp8uXtoa1kDqOsjP KXXpCWzXIpMrKIb2fNXvDkOdfA== X-Google-Smtp-Source: AH8x226vAkvFFRyvyiR1eirQrM+88k9UUzGjLZOkAZkZdiAVEib+u63ZS/LMgFYMpaY83mKLTTl/Pw== X-Received: by 10.223.169.161 with SMTP id b30mr2241912wrd.232.1519400212191; Fri, 23 Feb 2018 07:36:52 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:23 +0000 Message-Id: <20180223153636.29809-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 18/31] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This covers all the floating point convert operations. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 32 +++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 85 ++++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 4fd28fdf48..722fff2349 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -767,3 +767,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_stat= us) =20 return ret; } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} + +uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_uint16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index bc8d5b105b..32931b17c6 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -77,3 +77,5 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) +DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6f33663c7b..e3318837c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11240,6 +11240,46 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) only_in_vector =3D true; /* current rounding mode */ break; + case 0x1a: /* FCVTNS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x1b: /* FCVTMS */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x1c: /* FCVTAS */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x3a: /* FCVTPS */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x3b: /* FCVTZS */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; + case 0x5a: /* FCVTNU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEEVEN; + break; + case 0x5b: /* FCVTMU */ + need_rmode =3D true; + rmode =3D FPROUNDING_NEGINF; + break; + case 0x5c: /* FCVTAU */ + need_rmode =3D true; + rmode =3D FPROUNDING_TIEAWAY; + break; + case 0x7a: /* FCVTPU */ + need_rmode =3D true; + rmode =3D FPROUNDING_POSINF; + break; + case 0x7b: /* FCVTZU */ + need_rmode =3D true; + rmode =3D FPROUNDING_ZERO; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11273,7 +11313,36 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - /* no operations yet */ + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, 0, MO_16); + + switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + /* limit any sign extension going on */ + tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); } else { for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); @@ -11282,6 +11351,20 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); =20 switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatu= s); + break; case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 151940230856484.59473835541837; Fri, 23 Feb 2018 08:11:48 -0800 (PST) Received: from localhost ([::1]:45473 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFwp-0000zE-JV for importer@patchew.org; Fri, 23 Feb 2018 11:11:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46147) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFUp-00009i-9m for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFUn-0005yi-JQ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:51 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:37917) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFUn-0005x9-9i for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:49 -0500 Received: by mail-wm0-x242.google.com with SMTP id z9so5345612wmb.3 for ; Fri, 23 Feb 2018 07:42:49 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id o11sm2696294wra.28.2018.02.23.07.42.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:42:40 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id EF89F3E0CC8; Fri, 23 Feb 2018 15:36:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=quLuZZvfYOQqtY9r3MIBGGQuf0SjAevUKMOaZRnElbE=; b=IJgiDfewp2Oi0hpbjOKF/Jw/IDeFfJynpMhMiEG2lHOJiKCZFfozrrSrUvFc0qc3Lq BoVyOLU2GdowtP1wCXavTA18QbeZPgd4SiOwEse9v3boVeGLw869ueR8W0MuUDBxpOxd HvwJRC28hsmvcU3yq0TX/qu29TS1HQmDPMrd8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=quLuZZvfYOQqtY9r3MIBGGQuf0SjAevUKMOaZRnElbE=; b=A7wWIB9wCNr/ROTYYPqCwuJyAhVab8a7BRWXiZHGUeT3v2wrIwQjhsQu4PJTZWppx9 U/8bDd5J4CbvJ6f/IWPQ6GacNY7y09QPNqtvI9KobJp0QbVYVOzCnhypTQ9po55gPlqO l463nu4ER0Sx+N5Lrmp+KDwpyWIGTUHzC9ffG69pKkI8EWdLQr+nO9qUZKQwfXSKe38V bn5NOIaOVwO4G5M70CM/2hjV7Lqm1heXyoWBdLnxYEJrHCk+otLn+1SjCA4O4qEBuw1z HXZ97jccSMle/wG77ssCMzKvxQG3G1uv2fs/vu5DCy1CY8o+AvOxRa0KSLq82Crh33JO PdBQ== X-Gm-Message-State: APf1xPAyraONPq/WTwmQ5MQa7Tzh+ZeOMfMX701h/nJyVVlz5rl3RAQy LidOCXx/AjvsOtCb+XU5Ex0cQg== X-Google-Smtp-Source: AG47ELvwksLf8D6frHArlqSPT/HxIUUKaLfMrhGsiCukV1E4Yn6giCdE0HMHRurvyewnnRvjJuw7/A== X-Received: by 10.28.241.2 with SMTP id p2mr1947370wmh.105.1519400568173; Fri, 23 Feb 2018 07:42:48 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:24 +0000 Message-Id: <20180223153636.29809-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 19/31] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - use size directly wuth read/write_vec_element - drop unneeded break - WIP: mess with calculating maxpasses --- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 57 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e3318837c9..c251121c2b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7821,14 +7821,14 @@ static void handle_2misc_fcmp_zero(DisasContext *s,= int opcode, bool is_scalar, bool is_u, bool is_q, int size, int rn, int rd) { - bool is_double =3D (size =3D=3D 3); + bool is_double =3D (size =3D=3D MO_64); TCGv_ptr fpst; =20 if (!fp_access_check(s)) { return; } =20 - fpst =3D get_fpstatus_ptr(false); + fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); @@ -7880,34 +7880,57 @@ static void handle_2misc_fcmp_zero(DisasContext *s,= int opcode, bool swap =3D false; int pass, maxpasses; =20 - switch (opcode) { - case 0x2e: /* FCMLT (zero) */ - swap =3D true; - /* fall through */ - case 0x2c: /* FCMGT (zero) */ - genfn =3D gen_helper_neon_cgt_f32; - break; - case 0x2d: /* FCMEQ (zero) */ - genfn =3D gen_helper_neon_ceq_f32; - break; - case 0x6d: /* FCMLE (zero) */ - swap =3D true; - /* fall through */ - case 0x6c: /* FCMGE (zero) */ - genfn =3D gen_helper_neon_cge_f32; - break; - default: - g_assert_not_reached(); + if (size =3D=3D MO_16) { + switch (opcode) { + case 0x2e: /* FCMLT (zero) */ + swap =3D true; + /* fall through */ + case 0x2c: /* FCMGT (zero) */ + genfn =3D gen_helper_advsimd_cgt_f16; + break; + case 0x2d: /* FCMEQ (zero) */ + genfn =3D gen_helper_advsimd_ceq_f16; + break; + case 0x6d: /* FCMLE (zero) */ + swap =3D true; + /* fall through */ + case 0x6c: /* FCMGE (zero) */ + genfn =3D gen_helper_advsimd_cge_f16; + break; + default: + g_assert_not_reached(); + } + } else { + switch (opcode) { + case 0x2e: /* FCMLT (zero) */ + swap =3D true; + /* fall through */ + case 0x2c: /* FCMGT (zero) */ + genfn =3D gen_helper_neon_cgt_f32; + break; + case 0x2d: /* FCMEQ (zero) */ + genfn =3D gen_helper_neon_ceq_f32; + break; + case 0x6d: /* FCMLE (zero) */ + swap =3D true; + /* fall through */ + case 0x6c: /* FCMGE (zero) */ + genfn =3D gen_helper_neon_cge_f32; + break; + default: + g_assert_not_reached(); + } } =20 if (is_scalar) { maxpasses =3D 1; } else { - maxpasses =3D is_q ? 4 : 2; + int vector_size =3D 8 << is_q; + maxpasses =3D vector_size >> size; } =20 for (pass =3D 0; pass < maxpasses; pass++) { - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, size); if (swap) { genfn(tcg_res, tcg_zero, tcg_op, fpst); } else { @@ -7916,7 +7939,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, size); } } tcg_temp_free_i32(tcg_res); @@ -11209,7 +11232,18 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) fpop =3D deposit32(opcode, 5, 1, a); fpop =3D deposit32(fpop, 6, 1, u); =20 + rd =3D extract32(insn, 0, 5); + rn =3D extract32(insn, 5, 5); + switch (fpop) { + break; + case 0x2c: /* FCMGT (zero) */ + case 0x2d: /* FCMEQ (zero) */ + case 0x2e: /* FCMLT (zero) */ + case 0x6c: /* FCMGE (zero) */ + case 0x6d: /* FCMLE (zero) */ + handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); + return; case 0x18: /* FRINTN */ need_rmode =3D true; only_in_vector =3D true; --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++ target/arm/helper.h | 10 ++++ target/arm/translate-a64.c | 114 +++++++++++++++++++++++++++++++++++------= ---- 3 files changed, 104 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 303cd1eaf9..6e3dadb754 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11302,8 +11302,10 @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \ CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) =20 +FLOAT_CONVS(si, h, 16, ) FLOAT_CONVS(si, s, 32, ) FLOAT_CONVS(si, d, 64, ) +FLOAT_CONVS(ui, h, 16, u) FLOAT_CONVS(ui, s, 32, u) FLOAT_CONVS(ui, d, 64, u) =20 @@ -11386,6 +11388,8 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) VFP_CONV_FIX(uh, s, 32, 32, uint16) VFP_CONV_FIX(ul, s, 32, 32, uint32) VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) +VFP_CONV_FIX_A64(sl, h, 16, 32, int32) +VFP_CONV_FIX_A64(ul, h, 16, 32, uint32) #undef VFP_CONV_FIX #undef VFP_CONV_FIX_FLOAT #undef VFP_CONV_FLOAT_FIX_ROUND diff --git a/target/arm/helper.h b/target/arm/helper.h index 81ecb319b3..c0f35592ff 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -120,17 +120,23 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) =20 +DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, ptr) DEF_HELPER_2(vfp_uitod, f64, i32, ptr) +DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) DEF_HELPER_2(vfp_sitos, f32, i32, ptr) DEF_HELPER_2(vfp_sitod, f64, i32, ptr) =20 +DEF_HELPER_2(vfp_touih, i32, f16, ptr) DEF_HELPER_2(vfp_touis, i32, f32, ptr) DEF_HELPER_2(vfp_touid, i32, f64, ptr) +DEF_HELPER_2(vfp_touizh, i32, f16, ptr) DEF_HELPER_2(vfp_touizs, i32, f32, ptr) DEF_HELPER_2(vfp_touizd, i32, f64, ptr) +DEF_HELPER_2(vfp_tosih, i32, f16, ptr) DEF_HELPER_2(vfp_tosis, i32, f32, ptr) DEF_HELPER_2(vfp_tosid, i32, f64, ptr) +DEF_HELPER_2(vfp_tosizh, i32, f16, ptr) DEF_HELPER_2(vfp_tosizs, i32, f32, ptr) DEF_HELPER_2(vfp_tosizd, i32, f64, ptr) =20 @@ -142,6 +148,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, pt= r) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) @@ -166,6 +174,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) =20 DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c251121c2b..abe23f7d3f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6902,23 +6902,28 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, int elements, int is_signed, int fracbits, int size) { - bool is_double =3D size =3D=3D 3 ? true : false; - TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(false); - TCGv_i32 tcg_shift =3D tcg_const_i32(fracbits); - TCGv_i64 tcg_int =3D tcg_temp_new_i64(); + TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); + TCGv_i32 tcg_shift =3D NULL; + TCGMemOp mop =3D size | (is_signed ? MO_SIGN : 0); int pass; =20 - for (pass =3D 0; pass < elements; pass++) { - read_vec_element(s, tcg_int, rn, pass, mop); + if (fracbits || size =3D=3D MO_64) { + tcg_shift =3D tcg_const_i32(fracbits); + } + + if (size =3D=3D MO_64) { + TCGv_i64 tcg_int64 =3D tcg_temp_new_i64(); + TCGv_i64 tcg_double =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass < elements; pass++) { + read_vec_element(s, tcg_int64, rn, pass, mop); =20 - if (is_double) { - TCGv_i64 tcg_double =3D tcg_temp_new_i64(); if (is_signed) { - gen_helper_vfp_sqtod(tcg_double, tcg_int, + gen_helper_vfp_sqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } else { - gen_helper_vfp_uqtod(tcg_double, tcg_int, + gen_helper_vfp_uqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } if (elements =3D=3D 1) { @@ -6926,28 +6931,72 @@ static void handle_simd_intfp_conv(DisasContext *s,= int rd, int rn, } else { write_vec_element(s, tcg_double, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single =3D tcg_temp_new_i32(); - if (is_signed) { - gen_helper_vfp_sqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); - } else { - gen_helper_vfp_uqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); + } + + tcg_temp_free_i64(tcg_int64); + tcg_temp_free_i64(tcg_double); + + } else { + TCGv_i32 tcg_int32 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_float =3D tcg_temp_new_i32(); + + for (pass =3D 0; pass < elements; pass++) { + read_vec_element_i32(s, tcg_int32, rn, pass, mop); + + switch (size) { + case MO_32: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fps= t); + } else { + gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fps= t); + } + } + break; + case MO_16: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fps= t); + } else { + gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fps= t); + } + } + break; + default: + g_assert_not_reached(); } + if (elements =3D=3D 1) { - write_fp_sreg(s, rd, tcg_single); + write_fp_sreg(s, rd, tcg_float); } else { - write_vec_element_i32(s, tcg_single, rd, pass, MO_32); + write_vec_element_i32(s, tcg_float, rd, pass, size); } - tcg_temp_free_i32(tcg_single); } + + tcg_temp_free_i32(tcg_int32); + tcg_temp_free_i32(tcg_float); } =20 - tcg_temp_free_i64(tcg_int); tcg_temp_free_ptr(tcg_fpst); - tcg_temp_free_i32(tcg_shift); + if (tcg_shift) { + tcg_temp_free_i32(tcg_shift); + } =20 clear_vec_high(s, elements << size =3D=3D 16, rd); } @@ -11236,6 +11285,23 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) rn =3D extract32(insn, 5, 5); =20 switch (fpop) { + case 0x1d: /* SCVTF */ + case 0x5d: /* UCVTF */ + { + int elements; + + if (is_scalar) { + elements =3D 1; + } else { + elements =3D (is_q ? 8 : 4); + } + + if (!fp_access_check(s)) { + return; + } + handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); + return; + } break; case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401401691515.7957082330156; Fri, 23 Feb 2018 07:56:41 -0800 (PST) Received: from localhost ([::1]:45375 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFi9-0004KT-QL for importer@patchew.org; Fri, 23 Feb 2018 10:56:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFUa-0008K0-VQ for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1epFUa-0005V3-4E for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:37 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:50817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1epFUZ-0005To-TH for qemu-devel@nongnu.org; Fri, 23 Feb 2018 10:42:36 -0500 Received: by mail-wm0-x242.google.com with SMTP id k87so5458346wmi.0 for ; Fri, 23 Feb 2018 07:42:35 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id h188sm1806595wmf.23.2018.02.23.07.42.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 07:42:32 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 2160E3E1615; Fri, 23 Feb 2018 15:36:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M/ELSfnaMTKpBPvluZXv1czChxKQ/soVFuTcNVNN2Fg=; b=cjlJ6gFcspZNq4kTIdD1SbqEEvOMLY8NB0jyQKdB7t2FNok0RtCLXt81l2+HYx+mJR lBSmTpXMn3L2N02TdtGrZ48R1n9iBASSeA6EXGiPOWt4u6U2TRTfsPvPYPY/1Ovb9H7n BE5vXxLrcfU6Z3mAcWMqNo0C8iX3QFceICdvQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M/ELSfnaMTKpBPvluZXv1czChxKQ/soVFuTcNVNN2Fg=; b=ZGQNvSfTBQljXRN4/9yq0XGoiAF3+ipybWOmsMG/tBuuiHsTywzNxHHvLcVKH/nBeH SH7M69Jq1DxQQyD6BmrM1uIX08K/5cxYKsu97wbJTN/JQvnu/ETbvsjFS6DKUTdSevZS WKnIZWZTx8IfJNAkO+Nxm/bnkNdblzPq1iwwcwMgehlY/bTZUblXINNfd6Tt9B3lRfpw djmq0oVL4dyrFzmX93VZtdFndqEPLcViMz1E2vafTpxtdjn2UfNS0vrmo0B+0tkk/4ON jWXSdR9DYUtCHyBLW0n8kcfLRSydumEFhLwCPHpxhGKehHOtayBWNKbraEhrOOedVfIR yG4w== X-Gm-Message-State: APf1xPABwPojk7zCD5f3LdepVqERT/qfPVv5PVxdF9bIVInTIbA/ovS0 1UgVcRpJ2B0bVeBuDUL+CjY8Pw== X-Google-Smtp-Source: AG47ELt7+NuwHdfbWjqAd5Kpd0o/HBHPU1Uu0hKZSwFvrnbMniUKJXgCojGOc8JuFRo+A/cmyx0vyQ== X-Received: by 10.28.74.66 with SMTP id x63mr1914513wma.4.1519400554748; Fri, 23 Feb 2018 07:42:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:26 +0000 Message-Id: <20180223153636.29809-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Neither of these operations alter the floating point status registers so we can do a pure bitwise operation, either squashing any sign bit (ABS) or inverting it (NEG). Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - fixup re-base conflicts - make both operations pure bitwise TCG --- target/arm/translate-a64.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index abe23f7d3f..00b04d34f9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) TCGv_i32 tcg_rmode =3D NULL; TCGv_ptr tcg_fpstatus =3D NULL; bool need_rmode =3D false; + bool need_fpst =3D true; int rmode; =20 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { @@ -11380,6 +11381,10 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) need_rmode =3D true; rmode =3D FPROUNDING_ZERO; break; + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + need_fpst =3D false; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11403,7 +11408,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) return; } =20 - if (need_rmode) { + if (need_rmode || need_fpst) { tcg_fpstatus =3D get_fpstatus_ptr(true); } =20 @@ -11433,6 +11438,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } @@ -11476,6 +11484,12 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) case 0x59: /* FRINTX */ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstat= us); break; + case 0x2f: /* FABS */ + tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); + break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v3 22/31] arm/helper.c: re-factor recpe and add recepe_f16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - fix comment 2.0^-16 - f16_exp >=3D 29 (biased) - remove confusing comment about fpst --- target/arm/helper.c | 224 +++++++++++++++++++++++++++++-------------------= ---- target/arm/helper.h | 1 + 2 files changed, 128 insertions(+), 97 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6e3dadb754..e2d0ff0b4c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11523,80 +11523,75 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, = CPUARMState *env) * int->float conversions at run-time. */ #define float64_256 make_float64(0x4070000000000000LL) #define float64_512 make_float64(0x4080000000000000LL) +#define float16_maxnorm make_float16(0x7bff) #define float32_maxnorm make_float32(0x7f7fffff) #define float64_maxnorm make_float64(0x7fefffffffffffffLL) =20 /* Reciprocal functions * * The algorithm that must be used to calculate the estimate - * is specified by the ARM ARM, see FPRecipEstimate() + * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate */ =20 -static float64 recip_estimate(float64 a, float_status *real_fp_status) -{ - /* These calculations mustn't set any fp exception flags, - * so we use a local copy of the fp_status. - */ - float_status dummy_status =3D *real_fp_status; - float_status *s =3D &dummy_status; - /* q =3D (int)(a * 512.0) */ - float64 q =3D float64_mul(float64_512, a, s); - int64_t q_int =3D float64_to_int64_round_to_zero(q, s); - - /* r =3D 1.0 / (((double)q + 0.5) / 512.0) */ - q =3D int64_to_float64(q_int, s); - q =3D float64_add(q, float64_half, s); - q =3D float64_div(q, float64_512, s); - q =3D float64_div(float64_one, q, s); - - /* s =3D (int)(256.0 * r + 0.5) */ - q =3D float64_mul(q, float64_256, s); - q =3D float64_add(q, float64_half, s); - q_int =3D float64_to_int64_round_to_zero(q, s); +/* See RecipEstimate() + * + * input is a 9 bit fixed point number + * input range 256 .. 511 for a number from 0.5 <=3D x < 1.0. + * result range 256 .. 511 for a number from 1.0 to 511/256. + */ =20 - /* return (double)s / 256.0 */ - return float64_div(int64_to_float64(q_int, s), float64_256, s); +static int recip_estimate(int input) +{ + int a, b, r; + assert(256 <=3D input && input < 512); + a =3D (input * 2) + 1; + b =3D (1 << 19) / a; + r =3D (b + 1) >> 1; + assert(256 <=3D r && r < 512); + return r; } =20 -/* Common wrapper to call recip_estimate */ -static float64 call_recip_estimate(float64 num, int off, float_status *fps= t) +/* + * Common wrapper to call recip_estimate + * + * The parameters are exponent and 64 bit fraction (without implicit + * bit) where the binary point is nominally at bit 52. Returns a + * float64 which can then be rounded to the appropriate size by the + * callee. + */ + +static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) { - uint64_t val64 =3D float64_val(num); - uint64_t frac =3D extract64(val64, 0, 52); - int64_t exp =3D extract64(val64, 52, 11); - uint64_t sbit; - float64 scaled, estimate; + uint32_t scaled, estimate; + uint64_t result_frac; + int result_exp; =20 - /* Generate the scaled number for the estimate function */ - if (exp =3D=3D 0) { + /* Handle sub-normals */ + if (*exp =3D=3D 0) { if (extract64(frac, 51, 1) =3D=3D 0) { - exp =3D -1; - frac =3D extract64(frac, 0, 50) << 2; + *exp =3D -1; + frac <<=3D 2; } else { - frac =3D extract64(frac, 0, 51) << 1; + frac <<=3D 1; } } =20 - /* scaled =3D '0' : '01111111110' : fraction<51:44> : Zeros(44); */ - scaled =3D make_float64((0x3feULL << 52) - | extract64(frac, 44, 8) << 44); - - estimate =3D recip_estimate(scaled, fpst); + /* scaled =3D UInt('1':fraction<51:44>) */ + scaled =3D deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); + estimate =3D recip_estimate(scaled); =20 - /* Build new result */ - val64 =3D float64_val(estimate); - sbit =3D 0x8000000000000000ULL & val64; - exp =3D off - exp; - frac =3D extract64(val64, 0, 52); - - if (exp =3D=3D 0) { - frac =3D 1ULL << 51 | extract64(frac, 1, 51); - } else if (exp =3D=3D -1) { - frac =3D 1ULL << 50 | extract64(frac, 2, 50); - exp =3D 0; + result_exp =3D exp_off - *exp; + result_frac =3D deposit64(0, 44, 8, estimate); + if (result_exp =3D=3D 0) { + result_frac =3D deposit64(result_frac >> 1, 51, 1, 1); + } else if (result_exp =3D=3D -1) { + result_frac =3D deposit64(result_frac >> 2, 50, 2, 1); + result_exp =3D 0; } =20 - return make_float64(sbit | (exp << 52) | frac); + *exp =3D result_exp; + + return result_frac; } =20 static bool round_to_inf(float_status *fpst, bool sign_bit) @@ -11615,18 +11610,63 @@ static bool round_to_inf(float_status *fpst, bool= sign_bit) g_assert_not_reached(); } =20 +float16 HELPER(recpe_f16)(float16 input, void *fpstp) +{ + float_status *fpst =3D fpstp; + float16 f16 =3D float16_squash_input_denormal(input, fpst); + uint32_t f16_val =3D float16_val(f16); + uint32_t f16_sign =3D float16_is_neg(f16); + int f16_exp =3D extract32(f16_val, 10, 5); + uint32_t f16_frac =3D extract32(f16_val, 0, 10); + uint64_t f64_frac; + + if (float16_is_any_nan(f16)) { + float16 nan =3D f16; + if (float16_is_signaling_nan(f16, fpst)) { + float_raise(float_flag_invalid, fpst); + nan =3D float16_maybe_silence_nan(f16, fpst); + } + if (fpst->default_nan_mode) { + nan =3D float16_default_nan(fpst); + } + return nan; + } else if (float16_is_infinity(f16)) { + return float16_set_sign(float16_zero, float16_is_neg(f16)); + } else if (float16_is_zero(f16)) { + float_raise(float_flag_divbyzero, fpst); + return float16_set_sign(float16_infinity, float16_is_neg(f16)); + } else if (float16_abs(f16) < (1 << 8)) { + /* Abs(value) < 2.0^-16 */ + float_raise(float_flag_overflow | float_flag_inexact, fpst); + if (round_to_inf(fpst, f16_sign)) { + return float16_set_sign(float16_infinity, f16_sign); + } else { + return float16_set_sign(float16_maxnorm, f16_sign); + } + } else if (f16_exp >=3D 29 && fpst->flush_to_zero) { + float_raise(float_flag_underflow, fpst); + return float16_set_sign(float16_zero, float16_is_neg(f16)); + } + + f64_frac =3D call_recip_estimate(&f16_exp, 29, + ((uint64_t) f16_frac) << (52 - 10)); + + /* result =3D sign : result_exp<4:0> : fraction<51:42> */ + f16_val =3D deposit32(0, 15, 1, f16_sign); + f16_val =3D deposit32(f16_val, 10, 5, f16_exp); + f16_val =3D deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)= ); + return make_float16(f16_val); +} + float32 HELPER(recpe_f32)(float32 input, void *fpstp) { float_status *fpst =3D fpstp; float32 f32 =3D float32_squash_input_denormal(input, fpst); uint32_t f32_val =3D float32_val(f32); - uint32_t f32_sbit =3D 0x80000000ULL & f32_val; - int32_t f32_exp =3D extract32(f32_val, 23, 8); + bool f32_sign =3D float32_is_neg(f32); + int f32_exp =3D extract32(f32_val, 23, 8); uint32_t f32_frac =3D extract32(f32_val, 0, 23); - float64 f64, r64; - uint64_t r64_val; - int64_t r64_exp; - uint64_t r64_frac; + uint64_t f64_frac; =20 if (float32_is_any_nan(f32)) { float32 nan =3D f32; @@ -11643,30 +11683,27 @@ float32 HELPER(recpe_f32)(float32 input, void *fp= stp) } else if (float32_is_zero(f32)) { float_raise(float_flag_divbyzero, fpst); return float32_set_sign(float32_infinity, float32_is_neg(f32)); - } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { + } else if (float32_abs(f32) < (1ULL << 21)) { /* Abs(value) < 2.0^-128 */ float_raise(float_flag_overflow | float_flag_inexact, fpst); - if (round_to_inf(fpst, f32_sbit)) { - return float32_set_sign(float32_infinity, float32_is_neg(f32)); + if (round_to_inf(fpst, f32_sign)) { + return float32_set_sign(float32_infinity, f32_sign); } else { - return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); + return float32_set_sign(float32_maxnorm, f32_sign); } } else if (f32_exp >=3D 253 && fpst->flush_to_zero) { float_raise(float_flag_underflow, fpst); return float32_set_sign(float32_zero, float32_is_neg(f32)); } =20 + f64_frac =3D call_recip_estimate(&f32_exp, 253, + ((uint64_t) f32_frac) << (52 - 23)); =20 - f64 =3D make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) = << 29); - r64 =3D call_recip_estimate(f64, 253, fpst); - r64_val =3D float64_val(r64); - r64_exp =3D extract64(r64_val, 52, 11); - r64_frac =3D extract64(r64_val, 0, 52); - - /* result =3D sign : result_exp<7:0> : fraction<51:29>; */ - return make_float32(f32_sbit | - (r64_exp & 0xff) << 23 | - extract64(r64_frac, 29, 24)); + /* result =3D sign : result_exp<7:0> : fraction<51:29> */ + f32_val =3D deposit32(0, 31, 1, f32_sign); + f32_val =3D deposit32(f32_val, 23, 8, f32_exp); + f32_val =3D deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)= ); + return make_float32(f32_val); } =20 float64 HELPER(recpe_f64)(float64 input, void *fpstp) @@ -11674,12 +11711,9 @@ float64 HELPER(recpe_f64)(float64 input, void *fps= tp) float_status *fpst =3D fpstp; float64 f64 =3D float64_squash_input_denormal(input, fpst); uint64_t f64_val =3D float64_val(f64); - uint64_t f64_sbit =3D 0x8000000000000000ULL & f64_val; - int64_t f64_exp =3D extract64(f64_val, 52, 11); - float64 r64; - uint64_t r64_val; - int64_t r64_exp; - uint64_t r64_frac; + bool f64_sign =3D float64_is_neg(f64); + int f64_exp =3D extract64(f64_val, 52, 11); + uint64_t f64_frac =3D extract64(f64_val, 0, 52); =20 /* Deal with any special cases */ if (float64_is_any_nan(f64)) { @@ -11700,25 +11734,23 @@ float64 HELPER(recpe_f64)(float64 input, void *fp= stp) } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { /* Abs(value) < 2.0^-1024 */ float_raise(float_flag_overflow | float_flag_inexact, fpst); - if (round_to_inf(fpst, f64_sbit)) { - return float64_set_sign(float64_infinity, float64_is_neg(f64)); + if (round_to_inf(fpst, f64_sign)) { + return float64_set_sign(float64_infinity, f64_sign); } else { - return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); + return float64_set_sign(float64_maxnorm, f64_sign); } } else if (f64_exp >=3D 2045 && fpst->flush_to_zero) { float_raise(float_flag_underflow, fpst); return float64_set_sign(float64_zero, float64_is_neg(f64)); } =20 - r64 =3D call_recip_estimate(f64, 2045, fpst); - r64_val =3D float64_val(r64); - r64_exp =3D extract64(r64_val, 52, 11); - r64_frac =3D extract64(r64_val, 0, 52); + f64_frac =3D call_recip_estimate(&f64_exp, 2045, f64_frac); =20 - /* result =3D sign : result_exp<10:0> : fraction<51:0> */ - return make_float64(f64_sbit | - ((r64_exp & 0x7ff) << 52) | - r64_frac); + /* result =3D sign : result_exp<10:0> : fraction<51:0>; */ + f64_val =3D deposit64(0, 63, 1, f64_sign); + f64_val =3D deposit64(f64_val, 52, 11, f64_exp); + f64_val =3D deposit64(f64_val, 0, 52, f64_frac); + return make_float64(f64_val); } =20 /* The algorithm that must be used to calculate the estimate @@ -11907,19 +11939,17 @@ float64 HELPER(rsqrte_f64)(float64 input, void *f= pstp) =20 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) { - float_status *s =3D fpstp; - float64 f64; + /* float_status *s =3D fpstp; */ + int input, estimate; =20 if ((a & 0x80000000) =3D=3D 0) { return 0xffffffff; } =20 - f64 =3D make_float64((0x3feULL << 52) - | ((int64_t)(a & 0x7fffffff) << 21)); - - f64 =3D recip_estimate(f64, s); + input =3D extract32(a, 23, 9); + estimate =3D recip_estimate(input); =20 - return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); + return deposit32(0, (32 - 9), 9, estimate); } =20 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) diff --git a/target/arm/helper.h b/target/arm/helper.h index c0f35592ff..81d7baed6d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -192,6 +192,7 @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) =20 DEF_HELPER_3(recps_f32, f32, f32, f32, env) DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v3 23/31] arm/translate-a64: add FP16 FRECPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 00b04d34f9..56de5711fe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11311,6 +11311,8 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; + case 0x3d: /* FRECPE */ + break; case 0x18: /* FRINTN */ need_rmode =3D true; only_in_vector =3D true; @@ -11431,6 +11433,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ @@ -11466,6 +11471,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatu= s); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401757886471.9861980715242; Fri, 23 Feb 2018 08:02:37 -0800 (PST) Received: from localhost ([::1]:45409 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1epFnn-000155-2h for importer@patchew.org; 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Fri, 23 Feb 2018 07:42:39 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:29 +0000 Message-Id: <20180223153636.29809-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We go with the localised helper. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/helper-a64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 4 ++++ 3 files changed, 34 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 722fff2349..92a0d55a9c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -356,6 +356,35 @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a) } =20 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ +float16 HELPER(frecpx_f16)(float16 a, void *fpstp) +{ + float_status *fpst =3D fpstp; + uint16_t val16, sbit; + int16_t exp; + + if (float16_is_any_nan(a)) { + float16 nan =3D a; + if (float16_is_signaling_nan(a, fpst)) { + float_raise(float_flag_invalid, fpst); + nan =3D float16_maybe_silence_nan(a, fpst); + } + if (fpst->default_nan_mode) { + nan =3D float16_default_nan(fpst); + } + return nan; + } + + val16 =3D float16_val(a); + sbit =3D 0x8000 & val16; + exp =3D extract32(val16, 10, 5); + + if (exp =3D=3D 0) { + return make_float16(deposit32(sbit, 10, 5, 0x1e)); + } else { + return make_float16(deposit32(sbit, 10, 5, ~exp)); + } +} + float32 HELPER(frecpx_f32)(float32 a, void *fpstp) { float_status *fpst =3D fpstp; diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 32931b17c6..339323fc3d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -41,6 +41,7 @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i6= 4, i64) DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 56de5711fe..a7e99e2a2f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11312,6 +11312,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; case 0x3d: /* FRECPE */ + case 0x3f: /* FRECPX */ break; case 0x18: /* FRINTN */ need_rmode =3D true; @@ -11436,6 +11437,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x3d: /* FRECPE */ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3f: /* FRECPX */ + gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519402826893897.8344850441382; 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Fri, 23 Feb 2018 07:52:33 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:30 +0000 Message-Id: <20180223153636.29809-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v3 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 remove superfluous helpers --- target/arm/helper-a64.c | 13 +++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 5 +++++ 3 files changed, 19 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 92a0d55a9c..afb25ad20c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -828,3 +828,16 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *f= pstp) } return float16_to_uint16(a, fpst); } + +/* + * Square Root and Reciprocal square root + */ + +float16 HELPER(sqrt_f16)(float16 a, void *fpstp) +{ + float_status *s =3D fpstp; + + return float16_sqrt(a, s); +} + + diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 339323fc3d..ef4ddfe9d8 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -80,3 +80,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) +DEF_HELPER_2(sqrt_f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a7e99e2a2f..ba3926262e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11388,6 +11388,8 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst =3D false; break; + case 0x7f: /* FSQRT (vector) */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop= ); g_assert_not_reached(); @@ -11502,6 +11504,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7f: /* FSQRT */ + gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519401287969383.45454597031926; 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Fri, 23 Feb 2018 07:42:45 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:31 +0000 Message-Id: <20180223153636.29809-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes --- target/arm/helper.c | 221 ++++++++++++++++++++++++------------------------= ---- target/arm/helper.h | 1 + 2 files changed, 104 insertions(+), 118 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e2d0ff0b4c..c82f63d440 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11756,56 +11756,97 @@ float64 HELPER(recpe_f64)(float64 input, void *fp= stp) /* The algorithm that must be used to calculate the estimate * is specified by the ARM ARM. */ -static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) -{ - /* These calculations mustn't set any fp exception flags, - * so we use a local copy of the fp_status. - */ - float_status dummy_status =3D *real_fp_status; - float_status *s =3D &dummy_status; - float64 q; - int64_t q_int; - - if (float64_lt(a, float64_half, s)) { - /* range 0.25 <=3D a < 0.5 */ - - /* a in units of 1/512 rounded down */ - /* q0 =3D (int)(a * 512.0); */ - q =3D float64_mul(float64_512, a, s); - q_int =3D float64_to_int64_round_to_zero(q, s); - - /* reciprocal root r */ - /* r =3D 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ - q =3D int64_to_float64(q_int, s); - q =3D float64_add(q, float64_half, s); - q =3D float64_div(q, float64_512, s); - q =3D float64_sqrt(q, s); - q =3D float64_div(float64_one, q, s); + +static int do_recip_sqrt_estimate(int a) +{ + int b, estimate; + + assert(128 <=3D a && a < 512); + if (a < 256) { + a =3D a * 2 + 1; } else { - /* range 0.5 <=3D a < 1.0 */ + a =3D (a >> 1) << 1; + a =3D (a + 1) * 2; + } + b =3D 512; + while (a * (b + 1) * (b + 1) < (1 << 28)) { + b +=3D 1; + } + estimate =3D (b + 1) / 2; + assert(256 <=3D estimate && estimate < 512); + + return estimate; +} + =20 - /* a in units of 1/256 rounded down */ - /* q1 =3D (int)(a * 256.0); */ - q =3D float64_mul(float64_256, a, s); - int64_t q_int =3D float64_to_int64_round_to_zero(q, s); +static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) +{ + int estimate; + uint32_t scaled; =20 - /* reciprocal root r */ - /* r =3D 1.0 /sqrt(((double)q1 + 0.5) / 256); */ - q =3D int64_to_float64(q_int, s); - q =3D float64_add(q, float64_half, s); - q =3D float64_div(q, float64_256, s); - q =3D float64_sqrt(q, s); - q =3D float64_div(float64_one, q, s); + if (*exp =3D=3D 0) { + while (extract64(frac, 51, 1) =3D=3D 0) { + frac =3D frac << 1; + *exp -=3D 1; + } + frac =3D extract64(frac, 0, 51) << 1; } - /* r in units of 1/256 rounded to nearest */ - /* s =3D (int)(256.0 * r + 0.5); */ =20 - q =3D float64_mul(q, float64_256,s ); - q =3D float64_add(q, float64_half, s); - q_int =3D float64_to_int64_round_to_zero(q, s); + if (*exp & 1) { + /* scaled =3D UInt('01':fraction<51:45>) */ + scaled =3D deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); + } else { + /* scaled =3D UInt('1':fraction<51:44>) */ + scaled =3D deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); + } + estimate =3D do_recip_sqrt_estimate(scaled); =20 - /* return (double)s / 256.0;*/ - return float64_div(int64_to_float64(q_int, s), float64_256, s); + *exp =3D (exp_off - *exp) / 2; + return extract64(estimate, 0, 8) << 44; +} + +float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) +{ + float_status *s =3D fpstp; + float16 f16 =3D float16_squash_input_denormal(input, s); + uint16_t val =3D float16_val(f16); + bool f16_sign =3D float16_is_neg(f16); + int f16_exp =3D extract32(val, 10, 5); + uint16_t f16_frac =3D extract32(val, 0, 10); + uint64_t f64_frac; + + if (float16_is_any_nan(f16)) { + float16 nan =3D f16; + if (float16_is_signaling_nan(f16, s)) { + float_raise(float_flag_invalid, s); + nan =3D float16_maybe_silence_nan(f16, s); + } + if (s->default_nan_mode) { + nan =3D float16_default_nan(s); + } + return nan; + } else if (float16_is_zero(f16)) { + float_raise(float_flag_divbyzero, s); + return float16_set_sign(float16_infinity, f16_sign); + } else if (f16_sign) { + float_raise(float_flag_invalid, s); + return float16_default_nan(s); + } else if (float16_is_infinity(f16)) { + return float16_zero; + } + + /* Scale and normalize to a double-precision value between 0.25 and 1.= 0, + * preserving the parity of the exponent. */ + + f64_frac =3D ((uint64_t) f16_frac) << (52 - 10); + + f64_frac =3D recip_sqrt_estimate(&f16_exp, 44, f64_frac); + + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ + val =3D deposit32(0, 15, 1, f16_sign); + val =3D deposit32(val, 10, 5, f16_exp); + val =3D deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float16(val); } =20 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) @@ -11813,13 +11854,10 @@ float32 HELPER(rsqrte_f32)(float32 input, void *f= pstp) float_status *s =3D fpstp; float32 f32 =3D float32_squash_input_denormal(input, s); uint32_t val =3D float32_val(f32); - uint32_t f32_sbit =3D 0x80000000 & val; - int32_t f32_exp =3D extract32(val, 23, 8); + uint32_t f32_sign =3D float32_is_neg(f32); + int f32_exp =3D extract32(val, 23, 8); uint32_t f32_frac =3D extract32(val, 0, 23); uint64_t f64_frac; - uint64_t val64; - int result_exp; - float64 f64; =20 if (float32_is_any_nan(f32)) { float32 nan =3D f32; @@ -11845,32 +11883,13 @@ float32 HELPER(rsqrte_f32)(float32 input, void *f= pstp) * preserving the parity of the exponent. */ =20 f64_frac =3D ((uint64_t) f32_frac) << 29; - if (f32_exp =3D=3D 0) { - while (extract64(f64_frac, 51, 1) =3D=3D 0) { - f64_frac =3D f64_frac << 1; - f32_exp =3D f32_exp-1; - } - f64_frac =3D extract64(f64_frac, 0, 51) << 1; - } - - if (extract64(f32_exp, 0, 1) =3D=3D 0) { - f64 =3D make_float64(((uint64_t) f32_sbit) << 32 - | (0x3feULL << 52) - | f64_frac); - } else { - f64 =3D make_float64(((uint64_t) f32_sbit) << 32 - | (0x3fdULL << 52) - | f64_frac); - } =20 - result_exp =3D (380 - f32_exp) / 2; + f64_frac =3D recip_sqrt_estimate(&f32_exp, 380, f64_frac); =20 - f64 =3D recip_sqrt_estimate(f64, s); - - val64 =3D float64_val(f64); - - val =3D ((result_exp & 0xff) << 23) - | ((val64 >> 29) & 0x7fffff); + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ + val =3D deposit32(0, 31, 1, f32_sign); + val =3D deposit32(val, 23, 8, f32_exp); + val =3D deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); return make_float32(val); } =20 @@ -11879,11 +11898,9 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fp= stp) float_status *s =3D fpstp; float64 f64 =3D float64_squash_input_denormal(input, s); uint64_t val =3D float64_val(f64); - uint64_t f64_sbit =3D 0x8000000000000000ULL & val; - int64_t f64_exp =3D extract64(val, 52, 11); + bool f64_sign =3D float64_is_neg(f64); + int f64_exp =3D extract64(val, 52, 11); uint64_t f64_frac =3D extract64(val, 0, 52); - int64_t result_exp; - uint64_t result_frac; =20 if (float64_is_any_nan(f64)) { float64 nan =3D f64; @@ -11905,36 +11922,13 @@ float64 HELPER(rsqrte_f64)(float64 input, void *f= pstp) return float64_zero; } =20 - /* Scale and normalize to a double-precision value between 0.25 and 1.= 0, - * preserving the parity of the exponent. */ - - if (f64_exp =3D=3D 0) { - while (extract64(f64_frac, 51, 1) =3D=3D 0) { - f64_frac =3D f64_frac << 1; - f64_exp =3D f64_exp - 1; - } - f64_frac =3D extract64(f64_frac, 0, 51) << 1; - } + f64_frac =3D recip_sqrt_estimate(&f64_exp, 3068, f64_frac); =20 - if (extract64(f64_exp, 0, 1) =3D=3D 0) { - f64 =3D make_float64(f64_sbit - | (0x3feULL << 52) - | f64_frac); - } else { - f64 =3D make_float64(f64_sbit - | (0x3fdULL << 52) - | f64_frac); - } - - result_exp =3D (3068 - f64_exp) / 2; - - f64 =3D recip_sqrt_estimate(f64, s); - - result_frac =3D extract64(float64_val(f64), 0, 52); - - return make_float64(f64_sbit | - ((result_exp & 0x7ff) << 52) | - result_frac); + /* result =3D sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ + val =3D deposit64(0, 61, 1, f64_sign); + val =3D deposit64(val, 52, 11, f64_exp); + val =3D deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float64(val); } =20 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) @@ -11954,24 +11948,15 @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpst= p) =20 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) { - float_status *fpst =3D fpstp; - float64 f64; + int estimate; =20 if ((a & 0xc0000000) =3D=3D 0) { return 0xffffffff; } =20 - if (a & 0x80000000) { - f64 =3D make_float64((0x3feULL << 52) - | ((uint64_t)(a & 0x7fffffff) << 21)); - } else { /* bits 31-30 =3D=3D '01' */ - f64 =3D make_float64((0x3fdULL << 52) - | ((uint64_t)(a & 0x3fffffff) << 22)); - } - - f64 =3D recip_sqrt_estimate(f64, fpst); + estimate =3D do_recip_sqrt_estimate(extract32(a, 23, 9)); =20 - return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); + return deposit32(0, 23, 9, estimate); } =20 /* VFPv4 fused multiply-accumulate */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 81d7baed6d..6dd8504ec3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -195,6 +195,7 @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(recpe_u32, i32, i32, ptr) --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v3 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ba3926262e..faec8084fa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11388,6 +11388,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst =3D false; break; + case 0x7d: /* FRSQRTE */ case 0x7f: /* FSQRT (vector) */ break; default: @@ -11452,6 +11453,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -11504,6 +11508,9 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x7f: /* FSQRT */ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); break; --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 28/31] arm/translate-a64: add FP16 FMOV to simd_mod_imm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Only one half-precision instruction has been added to this group. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes v3 - use vfp_expand_imm --- target/arm/translate-a64.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index faec8084fa..806f2eb34a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6234,6 +6234,8 @@ static void disas_simd_copy(DisasContext *s, uint32_t= insn) * MVNI - move inverted (shifted) imm into register * ORR - bitwise OR of (shifted) imm with register * BIC - bitwise clear of (shifted) imm with register + * With ARMv8.2 we also have: + * FMOV half-precision */ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) { @@ -6248,8 +6250,11 @@ static void disas_simd_mod_imm(DisasContext *s, uint= 32_t insn) uint64_t imm =3D 0; =20 if (o2 !=3D 0 || ((cmode =3D=3D 0xf) && is_neg && !is_q)) { - unallocated_encoding(s); - return; + /* Check for FMOV (vector, immediate) - half-precision */ + if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode =3D=3D= 0xf)) { + unallocated_encoding(s); + return; + } } =20 if (!fp_access_check(s)) { @@ -6307,19 +6312,29 @@ static void disas_simd_mod_imm(DisasContext *s, uin= t32_t insn) imm |=3D 0x4000000000000000ULL; } } else { - imm =3D (abcdefgh & 0x3f) << 19; - if (abcdefgh & 0x80) { - imm |=3D 0x80000000; - } - if (abcdefgh & 0x40) { - imm |=3D 0x3e000000; + if (o2) { + /* FMOV (vector, immediate) - half-precision */ + imm =3D vfp_expand_imm(MO_16, abcdefgh); + /* now duplicate across the lanes */ + imm =3D bitfield_replicate(imm, 16); } else { - imm |=3D 0x40000000; + imm =3D (abcdefgh & 0x3f) << 19; + if (abcdefgh & 0x80) { + imm |=3D 0x80000000; + } + if (abcdefgh & 0x40) { + imm |=3D 0x3e000000; + } else { + imm |=3D 0x40000000; + } + imm |=3D (imm << 32); } - imm |=3D (imm << 32); } } break; + default: + fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); + g_assert_not_reached(); } =20 if (cmode_3_1 !=3D 7 && is_neg) { --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v3 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 I only needed to do a little light re-factoring to support the half-precision helpers. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 54 insertions(+), 26 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 806f2eb34a..6eae8bd8b1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6416,24 +6416,30 @@ static void disas_simd_scalar_pairwise(DisasContext= *s, uint32_t insn) case 0xf: /* FMAXP */ case 0x2c: /* FMINNMP */ case 0x2f: /* FMINP */ - /* FP op, size[0] is 32 or 64 bit */ + /* FP op, size[0] is 32 or 64 bit*/ if (!u) { - unallocated_encoding(s); - return; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } else { + size =3D MO_16; + } + } else { + size =3D extract32(size, 0, 1) ? MO_64 : MO_32; } + if (!fp_access_check(s)) { return; } =20 - size =3D extract32(size, 0, 1) ? 3 : 2; - fpst =3D get_fpstatus_ptr(false); + fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); break; default: unallocated_encoding(s); return; } =20 - if (size =3D=3D 3) { + if (size =3D=3D MO_64) { TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); TCGv_i64 tcg_op2 =3D tcg_temp_new_i64(); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); @@ -6474,27 +6480,49 @@ static void disas_simd_scalar_pairwise(DisasContext= *s, uint32_t insn) TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_32); - read_vec_element_i32(s, tcg_op2, rn, 1, MO_32); + read_vec_element_i32(s, tcg_op1, rn, 0, size); + read_vec_element_i32(s, tcg_op2, rn, 1, size); =20 - switch (opcode) { - case 0xc: /* FMAXNMP */ - gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xd: /* FADDP */ - gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xf: /* FMAXP */ - gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2c: /* FMINNMP */ - gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2f: /* FMINP */ - gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); - break; - default: - g_assert_not_reached(); + if (size =3D=3D MO_16) { + switch (opcode) { + case 0xc: /* FMAXNMP */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0xd: /* FADDP */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FMAXP */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2c: /* FMINNMP */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst= ); + break; + case 0x2f: /* FMINP */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + } else { + switch (opcode) { + case 0xc: /* FMAXNMP */ + gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xd: /* FADDP */ + gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FMAXP */ + gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2c: /* FMINNMP */ + gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2f: /* FMINP */ + gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } } =20 write_fp_sreg(s, rd, tcg_res); --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519400605519293.49746621072063; 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Fri, 23 Feb 2018 07:36:55 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Fri, 23 Feb 2018 15:36:35 +0000 Message-Id: <20180223153636.29809-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180223153636.29809-1-alex.bennee@linaro.org> References: <20180223153636.29809-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This covers the encoding group: Advanced SIMD scalar three same FP16 As all the helpers are already there it is simply a case of calling the existing helpers in the scalar context. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v2 - checkpatch fixes v3 - check for FP16 feature - remove stray debug - make abs a bitwise operation - checkpatch long line --- target/arm/translate-a64.c | 99 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 99 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6eae8bd8b1..6704d66be7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7802,6 +7802,104 @@ static void disas_simd_scalar_three_reg_same(DisasC= ontext *s, uint32_t insn) tcg_temp_free_i64(tcg_rd); } =20 +/* AdvSIMD scalar three same FP16 + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * v: 0101 1110 0100 0000 0000 0100 0000 0000 =3D> 5e400400 + * m: 1101 1111 0110 0000 1100 0100 0000 0000 =3D> df60c400 + */ +static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, + uint32_t insn) +{ + int rd =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int opcode =3D extract32(insn, 11, 3); + int rm =3D extract32(insn, 16, 5); + bool u =3D extract32(insn, 29, 1); + bool a =3D extract32(insn, 23, 1); + int fpopcode =3D opcode | (a << 3) | (u << 4); + TCGv_ptr fpst; + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + + switch (fpopcode) { + case 0x03: /* FMULX */ + case 0x04: /* FCMEQ (reg) */ + case 0x07: /* FRECPS */ + case 0x0f: /* FRSQRTS */ + case 0x14: /* FCMGE (reg) */ + case 0x15: /* FACGE */ + case 0x1a: /* FABD */ + case 0x1c: /* FCMGT (reg) */ + case 0x1d: /* FACGT */ + break; + default: + unallocated_encoding(s); + return; + } + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + } + + if (!fp_access_check(s)) { + return; + } + + fpst =3D get_fpstatus_ptr(true); + + tcg_op1 =3D tcg_temp_new_i32(); + tcg_op2 =3D tcg_temp_new_i32(); + tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); + read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); + + switch (fpopcode) { + case 0x03: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x04: /* FCMEQ (reg) */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x07: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x0f: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x14: /* FCMGE (reg) */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); + break; + case 0x1c: /* FCMGT (reg) */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_ptr(fpst); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -12654,6 +12752,7 @@ static const AArch64DecodeTable data_proc_simd[] = =3D { { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; =20 --=20 2.15.1 From nobody Wed Oct 22 12:56:34 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c0c::244 Subject: [Qemu-devel] [PATCH v3 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use existing helpers to achieve this. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- v3 - make fabs a bitwise operation - use read_vec_element_i32 to read value - properly wire into disas_fp_1rc --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 71 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6704d66be7..be2bf50ddb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4596,6 +4596,65 @@ static void disas_fp_csel(DisasContext *s, uint32_t = insn) tcg_temp_free_i64(t_true); } =20 +/* Floating-point data-processing (1 source) - half precision */ +static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int r= n) +{ + TCGv_ptr fpst =3D NULL; + TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_res =3D tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, 0, MO_16); + + switch (opcode) { + case 0x0: /* FMOV */ + tcg_gen_mov_i32(tcg_res, tcg_op); + break; + case 0x1: /* FABS */ + tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); + break; + case 0x2: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; + case 0x3: /* FSQRT */ + gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env); + break; + case 0x8: /* FRINTN */ + case 0x9: /* FRINTP */ + case 0xa: /* FRINTM */ + case 0xb: /* FRINTZ */ + case 0xc: /* FRINTA */ + { + TCGv_i32 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(opcode & 7)); + fpst =3D get_fpstatus_ptr(true); + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + break; + } + case 0xe: /* FRINTX */ + fpst =3D get_fpstatus_ptr(true); + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); + break; + case 0xf: /* FRINTI */ + fpst =3D get_fpstatus_ptr(true); + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); + break; + default: + abort(); + } + + write_fp_sreg(s, rd, tcg_res); + + if (fpst) { + tcg_temp_free_ptr(fpst); + } + tcg_temp_free_i32(tcg_op); + tcg_temp_free_i32(tcg_res); +} + /* Floating-point data-processing (1 source) - single precision */ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int= rn) { @@ -4825,6 +4884,18 @@ static void disas_fp_1src(DisasContext *s, uint32_t = insn) =20 handle_fp_1src_double(s, opcode, rd, rn); break; + case 3: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + handle_fp_1src_half(s, opcode, rd, rn); + break; default: unallocated_encoding(s); } --=20 2.15.1