From nobody Mon Feb 9 08:56:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1519313268432204.77794030480754; Thu, 22 Feb 2018 07:27:48 -0800 (PST) Received: from localhost ([::1]:38989 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eosmh-0008Pi-BT for importer@patchew.org; Thu, 22 Feb 2018 10:27:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eosiV-0004hI-HY for qemu-devel@nongnu.org; Thu, 22 Feb 2018 10:23:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eosiP-0001XT-MR for qemu-devel@nongnu.org; Thu, 22 Feb 2018 10:23:27 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46584) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eosiP-0001RM-Dm for qemu-devel@nongnu.org; Thu, 22 Feb 2018 10:23:21 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eosiL-00020I-Ui for qemu-devel@nongnu.org; Thu, 22 Feb 2018 15:23:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 22 Feb 2018 15:22:36 +0000 Message-Id: <20180222152307.7499-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180222152307.7499-1-peter.maydell@linaro.org> References: <20180222152307.7499-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/32] target/arm: Fix register definitions for VMIDR and VMPIDR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The register definitions for VMIDR and VMPIDR have separate reginfo structs for the AArch32 and AArch64 registers. However the 32-bit versions are wrong: * they use offsetof instead of offsetoflow32 to mark where the 32-bit value lives in the uint64_t CPU state field * they don't mark themselves as ARM_CP_ALIAS In particular this means that if you try to use an Arm guest CPU which enables EL2 on a big-endian host it will assert at reset: target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue =3D=3D newva= lue' failed. because the reset of the 32-bit register writes to the top half of the uint64_t. Correct the errors in the structures. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- This is necessary for 'make check' to pass on big endian systems with the 'raspi3' board enabled, which is the first board which has an EL2-enabled-by-default CPU. --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 32e4fd4732..c5bc69b961 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5069,8 +5069,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL2_RW, .resetvalue =3D cpu->midr, @@ -5078,8 +5078,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D vmpidr_def, - .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, + .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, .access =3D PL2_RW, --=20 2.16.1