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X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 07/19] target/hppa: Convert arithmetic/logical insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 337 ++++++++++++++++++++++---------------------= ---- target/hppa/insns.decode | 40 ++++++ 2 files changed, 197 insertions(+), 180 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ca46e8d50b..91617bf9ad 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1223,6 +1223,20 @@ static void do_add(DisasContext *ctx, unsigned rt, T= CGv_reg in1, ctx->null_cond =3D cond; } =20 +static void do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, + bool is_l, bool is_tsv, bool is_tc, bool is_c) +{ + TCGv_reg tcg_r1, tcg_r2; + + if (a->cf) { + nullify_over(ctx); + } + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); + do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a-= >cf); + nullify_end(ctx); +} + static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf) @@ -1289,6 +1303,20 @@ static void do_sub(DisasContext *ctx, unsigned rt, T= CGv_reg in1, ctx->null_cond =3D cond; } =20 +static void do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, + bool is_tsv, bool is_b, bool is_tc) +{ + TCGv_reg tcg_r1, tcg_r2; + + if (a->cf) { + nullify_over(ctx); + } + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); + do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); + nullify_end(ctx); +} + static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, unsigned cf) { @@ -1334,6 +1362,20 @@ static void do_log(DisasContext *ctx, unsigned rt, T= CGv_reg in1, } } =20 +static void do_log_reg(DisasContext *ctx, arg_rrr_cf *a, + void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) +{ + TCGv_reg tcg_r1, tcg_r2; + + if (a->cf) { + nullify_over(ctx); + } + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); + do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); + nullify_end(ctx); +} + static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, unsigned cf, bool is_tc, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) @@ -2475,129 +2517,85 @@ static void trans_lci(DisasContext *ctx, arg_lci *= a, uint32_t insn) cond_free(&ctx->null_cond); } =20 -static void trans_add(DisasContext *ctx, uint32_t insn, const DisasInsn *d= i) +static void trans_add(DisasContext *ctx, arg_rrr_cf_sh *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned ext =3D extract32(insn, 8, 4); - unsigned shift =3D extract32(insn, 6, 2); - unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tcg_r1, tcg_r2; - bool is_c =3D false; - bool is_l =3D false; - bool is_tc =3D false; - bool is_tsv =3D false; - - switch (ext) { - case 0x6: /* ADD, SHLADD */ - break; - case 0xa: /* ADD,L, SHLADD,L */ - is_l =3D true; - break; - case 0xe: /* ADD,TSV, SHLADD,TSV (1) */ - is_tsv =3D true; - break; - case 0x7: /* ADD,C */ - is_c =3D true; - break; - case 0xf: /* ADD,C,TSV */ - is_c =3D is_tsv =3D true; - break; - default: - gen_illegal(ctx); - return; - } - - if (cf) { - nullify_over(ctx); - } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_add(ctx, rt, tcg_r1, tcg_r2, shift, is_l, is_tsv, is_tc, is_c, cf); - nullify_end(ctx); + do_add_reg(ctx, a, false, false, false, false); } =20 -static void trans_sub(DisasContext *ctx, uint32_t insn, const DisasInsn *d= i) +static void trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned ext =3D extract32(insn, 6, 6); - unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tcg_r1, tcg_r2; - bool is_b =3D false; - bool is_tc =3D false; - bool is_tsv =3D false; - - switch (ext) { - case 0x10: /* SUB */ - break; - case 0x30: /* SUB,TSV */ - is_tsv =3D true; - break; - case 0x14: /* SUB,B */ - is_b =3D true; - break; - case 0x34: /* SUB,B,TSV */ - is_b =3D is_tsv =3D true; - break; - case 0x13: /* SUB,TC */ - is_tc =3D true; - break; - case 0x33: /* SUB,TSV,TC */ - is_tc =3D is_tsv =3D true; - break; - default: - return gen_illegal(ctx); - } - - if (cf) { - nullify_over(ctx); - } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_sub(ctx, rt, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, cf); - nullify_end(ctx); + do_add_reg(ctx, a, true, false, false, false); } =20 -static void trans_log(DisasContext *ctx, uint32_t insn, const DisasInsn *d= i) +static void trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a, uint32_t in= sn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tcg_r1, tcg_r2; - - if (cf) { - nullify_over(ctx); - } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_log(ctx, rt, tcg_r1, tcg_r2, cf, di->f.ttt); - nullify_end(ctx); + do_add_reg(ctx, a, false, true, false, false); } =20 -static void trans_or(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static void trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned rt =3D extract32(insn, 0, 5); - TCGv_reg tcg_r1, tcg_r2; + do_add_reg(ctx, a, false, false, false, true); +} =20 - if (cf =3D=3D 0) { - if (rt =3D=3D 0) { /* NOP */ +static void trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a, uint32_t = insn) +{ + do_add_reg(ctx, a, false, true, false, true); +} + +static void trans_sub(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_sub_reg(ctx, a, false, false, false); +} + +static void trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_sub_reg(ctx, a, true, false, false); +} + +static void trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_sub_reg(ctx, a, false, false, true); +} + +static void trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a, uint32_t in= sn) +{ + do_sub_reg(ctx, a, true, false, true); +} + +static void trans_sub_b(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_sub_reg(ctx, a, false, true, false); +} + +static void trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a, uint32_t ins= n) +{ + do_sub_reg(ctx, a, true, true, false); +} + +static void trans_andcm(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_log_reg(ctx, a, tcg_gen_andc_reg); +} + +static void trans_and(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_log_reg(ctx, a, tcg_gen_and_reg); +} + +static void trans_or(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + if (a->cf =3D=3D 0) { + if (a->t =3D=3D 0) { /* NOP */ cond_free(&ctx->null_cond); return; } - if (r2 =3D=3D 0) { /* COPY */ - if (r1 =3D=3D 0) { - TCGv_reg dest =3D dest_gpr(ctx, rt); + if (a->r2 =3D=3D 0) { /* COPY */ + if (a->r1 =3D=3D 0) { + TCGv_reg dest =3D dest_gpr(ctx, a->t); tcg_gen_movi_reg(dest, 0); - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); } else { - save_gpr(ctx, rt, cpu_gr[r1]); + save_gpr(ctx, a->t, cpu_gr[a->r1]); } cond_free(&ctx->null_cond); return; @@ -2609,7 +2607,8 @@ static void trans_or(DisasContext *ctx, uint32_t insn= , const DisasInsn *di) * or %r31,%r31,%r31 -- death loop; offline cpu * currently implemented as idle. */ - if ((rt =3D=3D 10 || rt =3D=3D 31) && r1 =3D=3D rt && r2 =3D=3D rt= ) { /* PAUSE */ + if ((a->t =3D=3D 10 || a->t =3D=3D 31) + && a->r1 =3D=3D a->t && a->r2 =3D=3D a->t) { /* PAUSE */ TCGv_i32 tmp; =20 /* No need to check for supervisor, as userland can only pause @@ -2634,76 +2633,67 @@ static void trans_or(DisasContext *ctx, uint32_t in= sn, const DisasInsn *di) } #endif } - - if (cf) { - nullify_over(ctx); - } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_log(ctx, rt, tcg_r1, tcg_r2, cf, tcg_gen_or_reg); - nullify_end(ctx); + do_log_reg(ctx, a, tcg_gen_or_reg); } =20 -static void trans_cmpclr(DisasContext *ctx, uint32_t insn, const DisasInsn= *di) +static void trans_xor(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_log_reg(ctx, a, tcg_gen_xor_reg); +} + +static void trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned rt =3D extract32(insn, 0, 5); TCGv_reg tcg_r1, tcg_r2; =20 - if (cf) { + if (a->cf) { nullify_over(ctx); } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_cmpclr(ctx, rt, tcg_r1, tcg_r2, cf); + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); + do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); nullify_end(ctx); } =20 -static void trans_uxor(DisasContext *ctx, uint32_t insn, const DisasInsn *= di) +static void trans_uxor(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned rt =3D extract32(insn, 0, 5); TCGv_reg tcg_r1, tcg_r2; =20 - if (cf) { + if (a->cf) { nullify_over(ctx); } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); - do_unit(ctx, rt, tcg_r1, tcg_r2, cf, false, tcg_gen_xor_reg); + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); nullify_end(ctx); } =20 -static void trans_uaddcm(DisasContext *ctx, uint32_t insn, const DisasInsn= *di) +static void do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned is_tc =3D extract32(insn, 6, 1); - unsigned rt =3D extract32(insn, 0, 5); TCGv_reg tcg_r1, tcg_r2, tmp; =20 - if (cf) { + if (a->cf) { nullify_over(ctx); } - tcg_r1 =3D load_gpr(ctx, r1); - tcg_r2 =3D load_gpr(ctx, r2); + tcg_r1 =3D load_gpr(ctx, a->r1); + tcg_r2 =3D load_gpr(ctx, a->r2); tmp =3D get_temp(ctx); tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, rt, tcg_r1, tmp, cf, is_tc, tcg_gen_add_reg); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); nullify_end(ctx); } =20 -static void trans_dcor(DisasContext *ctx, uint32_t insn, const DisasInsn *= di) +static void trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_uaddcm(ctx, a, false); +} + +static void trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a, uint32_t ins= n) +{ + do_uaddcm(ctx, a, true); +} + +static void do_dcor(DisasContext *ctx, arg_rrr_cf *a, bool is_i) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned is_i =3D extract32(insn, 6, 1); - unsigned rt =3D extract32(insn, 0, 5); TCGv_reg tmp; =20 nullify_over(ctx); @@ -2715,24 +2705,30 @@ static void trans_dcor(DisasContext *ctx, uint32_t = insn, const DisasInsn *di) } tcg_gen_andi_reg(tmp, tmp, 0x11111111); tcg_gen_muli_reg(tmp, tmp, 6); - do_unit(ctx, rt, tmp, load_gpr(ctx, r2), cf, false, + do_unit(ctx, a->t, tmp, load_gpr(ctx, a->r2), a->cf, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); =20 nullify_end(ctx); } =20 -static void trans_ds(DisasContext *ctx, uint32_t insn, const DisasInsn *di) +static void trans_dcor(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_dcor(ctx, a, false); +} + +static void trans_dcor_i(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) +{ + do_dcor(ctx, a, true); +} + +static void trans_ds(DisasContext *ctx, arg_rrr_cf *a, uint32_t insn) { - unsigned r2 =3D extract32(insn, 21, 5); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned cf =3D extract32(insn, 12, 4); - unsigned rt =3D extract32(insn, 0, 5); TCGv_reg dest, add1, add2, addc, zero, in1, in2; =20 nullify_over(ctx); =20 - in1 =3D load_gpr(ctx, r1); - in2 =3D load_gpr(ctx, r2); + in1 =3D load_gpr(ctx, a->r1); + in2 =3D load_gpr(ctx, a->r2); =20 add1 =3D tcg_temp_new(); add2 =3D tcg_temp_new(); @@ -2759,7 +2755,7 @@ static void trans_ds(DisasContext *ctx, uint32_t insn= , const DisasInsn *di) tcg_temp_free(zero); =20 /* Write back the result register. */ - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Write back PSW[CB]. */ tcg_gen_xor_reg(cpu_psw_cb, add1, add2); @@ -2770,13 +2766,13 @@ static void trans_ds(DisasContext *ctx, uint32_t in= sn, const DisasInsn *di) tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ - if (cf) { + if (a->cf) { TCGv_reg sv =3D NULL; - if (cf >> 1 =3D=3D 6) { + if (a->cf >> 1 =3D=3D 6) { /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(cf, dest, cpu_psw_cb_msb, sv); + ctx->null_cond =3D do_cond(a->cf, dest, cpu_psw_cb_msb, sv); } =20 tcg_temp_free(add1); @@ -2786,22 +2782,6 @@ static void trans_ds(DisasContext *ctx, uint32_t ins= n, const DisasInsn *di) nullify_end(ctx); } =20 -static const DisasInsn table_arith_log[] =3D { - { 0x08000240u, 0xfc000fe0u, trans_or }, - { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_andc_reg }, - { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_and_reg }, - { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt =3D tcg_gen_xor_reg }, - { 0x08000880u, 0xfc000fe0u, trans_cmpclr }, - { 0x08000380u, 0xfc000fe0u, trans_uxor }, - { 0x08000980u, 0xfc000fa0u, trans_uaddcm }, - { 0x08000b80u, 0xfc1f0fa0u, trans_dcor }, - { 0x08000440u, 0xfc000fe0u, trans_ds }, - { 0x08000700u, 0xfc0007e0u, trans_add }, /* add */ - { 0x08000400u, 0xfc0006e0u, trans_sub }, /* sub; sub,b; sub,tsv */ - { 0x080004c0u, 0xfc0007e0u, trans_sub }, /* sub,tc; sub,tsv,tc */ - { 0x08000200u, 0xfc000320u, trans_add }, /* shladd */ -}; - static void trans_addi(DisasContext *ctx, uint32_t insn) { target_sreg im =3D low_sextract(insn, 0, 11); @@ -4465,9 +4445,6 @@ static void translate_one(DisasContext *ctx, uint32_t= insn) =20 opc =3D extract32(insn, 26, 6); switch (opc) { - case 0x02: - translate_table(ctx, insn, table_arith_log); - return; case 0x03: translate_table(ctx, insn, table_index_mem); return; diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 5fe7b9a027..156a34bf1a 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -33,6 +33,17 @@ # All insns that need to form a virtual address should use this set. &ldst t b x disp sp m scale size =20 +&rrr_cf t r1 r2 cf +&rrr_cf_sh t r1 r2 cf sh + +#### +# Format definitions +#### + +@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf +@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh +@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 + #### # System #### @@ -87,3 +98,32 @@ lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ &ldst disp=3D0 scale=3D0 size=3D0 =20 lci 000001 ----- ----- -- 01001100 0 t:5 + +#### +# Arith/Log +#### + +andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf +and 000010 ..... ..... .... 001000 0 ..... @rrr_cf +or 000010 ..... ..... .... 001001 0 ..... @rrr_cf +xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf +uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf +ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf +cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf +uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf +uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf +dcor 000010 ..... ..... .... 101110 0 ..... @rrr_cf +dcor_i 000010 ..... ..... .... 101111 0 ..... @rrr_cf + +add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh +add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh +add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh +add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 +add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 + +sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf +sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf +sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf +sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf +sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf +sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf --=20 2.14.3