From nobody Mon Feb 9 14:46:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518900351207160.12720521970425; Sat, 17 Feb 2018 12:45:51 -0800 (PST) Received: from localhost ([::1]:60492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en9Mk-0003tO-9G for importer@patchew.org; Sat, 17 Feb 2018 15:45:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en99L-0000GA-41 for qemu-devel@nongnu.org; Sat, 17 Feb 2018 15:32:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1en99H-0000oD-V5 for qemu-devel@nongnu.org; Sat, 17 Feb 2018 15:31:59 -0500 Received: from mail-pl0-x244.google.com ([2607:f8b0:400e:c01::244]:45794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1en99H-0000o0-Ko for qemu-devel@nongnu.org; Sat, 17 Feb 2018 15:31:55 -0500 Received: by mail-pl0-x244.google.com with SMTP id p5so3525963plo.12 for ; Sat, 17 Feb 2018 12:31:55 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id y7sm48203797pfe.26.2018.02.17.12.31.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Feb 2018 12:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=2mq+ETVNhI2/MSGYKVSIowfW29RsgbWzsze1aqiBs7M=; b=G9doFhryAzzednscQTfDRGQWwfcqHhkEJn7rrFeNPh/6ATrtmKz3SDvvKW18NVp/Re x3tJA8xKqyUCl8ACU35nvd4QIA+PpnFtQS8J8UDCIJO5cTq8QZwiW6MAXeNvLVzkYIWh PSJ9JhDw5Tr3+cfBEl8S/4w7aHKoGvSVxGLNg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2mq+ETVNhI2/MSGYKVSIowfW29RsgbWzsze1aqiBs7M=; b=Jn2MYMV6myLwb8hoc9RE1F41WVQhbtgCtBKrbNiyBLinbn92t9I+oYC+8nxSEaY4VN woJxaspNu8dGQ5E54QKLr6n5dRrNmAjJGCeRjopCaux3dsteZ0qL5di1wSv1RHDEroYn qmCg4QHtB5pKx7U43g/24TSz3R3p+duclE1HPFjsDFjWHQ/3P+S6bZNZzCEvaXR9pA+o ovF3JIj3swjjNY3/znxd6KQ5jC7VVTsV3wAFTP1vMBiNLZ7AfY+kl12lzNhr0gkRIE2u sYQ0VZKoi4ZtWZ1ds/iRkQck+5XBA6p5RZ4y5j/h5dPgP6o3ieDffRsUaUqE1jvN6Ev5 CO0A== X-Gm-Message-State: APf1xPC26whgC2bTdP1s7GTMv7Vq4JmaDiqhoHmHZxXGXef4wAEQi/YY l6yIs7tm+RofDTsqBSn5U9o1UQ7U3Z4= X-Google-Smtp-Source: AH8x226AOfkku4ooqqeSIXymacy71RzPy/rSS+jvlwct3RwZQAYO2SYS4ZzFwpdZnYrrIkBSc23zyg== X-Received: by 2002:a17:902:724b:: with SMTP id c11-v6mr316873pll.352.1518899514270; Sat, 17 Feb 2018 12:31:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 12:31:24 -0800 Message-Id: <20180217203132.31780-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180217203132.31780-1-richard.henderson@linaro.org> References: <20180217203132.31780-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 11/19] target/hppa: Convert shift, extract, deposit insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 217 ++++++++++++++++++-------------------------= ---- target/hppa/insns.decode | 15 ++++ 2 files changed, 96 insertions(+), 136 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 361a20b733..e01a28c70c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3293,26 +3293,21 @@ static void trans_movbi(DisasContext *ctx, arg_movb= i *a, uint32_t insn) do_cbranch(ctx, a->disp, a->n, &cond); } =20 -static void trans_shrpw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a, uint32_t = insn) { - unsigned rt =3D extract32(insn, 0, 5); - unsigned c =3D extract32(insn, 13, 3); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned r2 =3D extract32(insn, 21, 5); TCGv_reg dest; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - if (r1 =3D=3D 0) { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, r2)); + dest =3D dest_gpr(ctx, a->t); + if (a->r1 =3D=3D 0) { + tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); tcg_gen_shr_reg(dest, dest, cpu_sar); - } else if (r1 =3D=3D r2) { + } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, r2)); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); @@ -3320,7 +3315,7 @@ static void trans_shrpw_sar(DisasContext *ctx, uint32= _t insn, TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 - tcg_gen_concat_reg_i64(t, load_gpr(ctx, r2), load_gpr(ctx, r1)); + tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); @@ -3328,79 +3323,67 @@ static void trans_shrpw_sar(DisasContext *ctx, uint= 32_t insn, tcg_temp_free_i64(t); tcg_temp_free_i64(s); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static void trans_shrpw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a, uint32_t = insn) { - unsigned rt =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned c =3D extract32(insn, 13, 3); - unsigned r1 =3D extract32(insn, 16, 5); - unsigned r2 =3D extract32(insn, 21, 5); - unsigned sa =3D 31 - cpos; + unsigned sa =3D 31 - a->cpos; TCGv_reg dest, t2; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - t2 =3D load_gpr(ctx, r2); - if (r1 =3D=3D r2) { + dest =3D dest_gpr(ctx, a->t); + t2 =3D load_gpr(ctx, a->r2); + if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); tcg_gen_extu_i32_reg(dest, t32); tcg_temp_free_i32(t32); - } else if (r1 =3D=3D 0) { + } else if (a->r1 =3D=3D 0) { tcg_gen_extract_reg(dest, t2, sa, 32 - sa); } else { TCGv_reg t0 =3D tcg_temp_new(); tcg_gen_extract_reg(t0, t2, sa, 32 - sa); - tcg_gen_deposit_reg(dest, t0, cpu_gr[r1], 32 - sa, sa); + tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa); tcg_temp_free(t0); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static void trans_extrw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a, uint32_t = insn) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned is_se =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 16, 5); - unsigned rr =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; + unsigned len =3D 32 - a->clen; TCGv_reg dest, src, tmp; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - src =3D load_gpr(ctx, rr); + dest =3D dest_gpr(ctx, a->t); + src =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); - if (is_se) { + if (a->se) { tcg_gen_sar_reg(dest, src, tmp); tcg_gen_sextract_reg(dest, dest, 0, len); } else { @@ -3408,83 +3391,62 @@ static void trans_extrw_sar(DisasContext *ctx, uint= 32_t insn, tcg_gen_extract_reg(dest, dest, 0, len); } tcg_temp_free(tmp); - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static void trans_extrw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a, uint32_t = insn) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned pos =3D extract32(insn, 5, 5); - unsigned is_se =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 16, 5); - unsigned rr =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; - unsigned cpos =3D 31 - pos; + unsigned len =3D 32 - a->clen; + unsigned cpos =3D 31 - a->pos; TCGv_reg dest, src; =20 - if (c) { + if (a->c) { nullify_over(ctx); } =20 - dest =3D dest_gpr(ctx, rt); - src =3D load_gpr(ctx, rr); - if (is_se) { + dest =3D dest_gpr(ctx, a->t); + src =3D load_gpr(ctx, a->r); + if (a->se) { tcg_gen_sextract_reg(dest, src, cpos, len); } else { tcg_gen_extract_reg(dest, src, cpos, len); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static const DisasInsn table_sh_ex[] =3D { - { 0xd0000000u, 0xfc001fe0u, trans_shrpw_sar }, - { 0xd0000800u, 0xfc001c00u, trans_shrpw_imm }, - { 0xd0001000u, 0xfc001be0u, trans_extrw_sar }, - { 0xd0001800u, 0xfc001800u, trans_extrw_imm }, -}; - -static void trans_depw_imm_c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a, uint32_t = insn) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - target_sreg val =3D low_sextract(insn, 16, 5); - unsigned rt =3D extract32(insn, 21, 5); - unsigned len =3D 32 - clen; + unsigned len =3D 32 - a->clen; target_sreg mask0, mask1; TCGv_reg dest; =20 - if (c) { + if (a->c) { nullify_over(ctx); } - if (cpos + len > 32) { - len =3D 32 - cpos; + if (a->cpos + len > 32) { + len =3D 32 - a->cpos; } =20 - dest =3D dest_gpr(ctx, rt); - mask0 =3D deposit64(0, cpos, len, val); - mask1 =3D deposit64(-1, cpos, len, val); + dest =3D dest_gpr(ctx, a->t); + mask0 =3D deposit64(0, a->cpos, len, a->i); + mask1 =3D deposit64(-1, a->cpos, len, a->i); =20 - if (nz) { - TCGv_reg src =3D load_gpr(ctx, rt); + if (a->nz) { + TCGv_reg src =3D load_gpr(ctx, a->t); if (mask1 !=3D -1) { tcg_gen_andi_reg(dest, src, mask1); src =3D dest; @@ -3493,75 +3455,58 @@ static void trans_depw_imm_c(DisasContext *ctx, uin= t32_t insn, } else { tcg_gen_movi_reg(dest, mask0); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static void trans_depw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void trans_depw_imm(DisasContext *ctx, arg_depw_imm *a, uint32_t in= sn) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned cpos =3D extract32(insn, 5, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rr =3D extract32(insn, 16, 5); - unsigned rt =3D extract32(insn, 21, 5); - unsigned rs =3D nz ? rt : 0; - unsigned len =3D 32 - clen; + unsigned rs =3D a->nz ? a->t : 0; + unsigned len =3D 32 - a->clen; TCGv_reg dest, val; =20 - if (c) { + if (a->c) { nullify_over(ctx); } - if (cpos + len > 32) { - len =3D 32 - cpos; + if (a->cpos + len > 32) { + len =3D 32 - a->cpos; } =20 - dest =3D dest_gpr(ctx, rt); - val =3D load_gpr(ctx, rr); + dest =3D dest_gpr(ctx, a->t); + val =3D load_gpr(ctx, a->r); if (rs =3D=3D 0) { - tcg_gen_deposit_z_reg(dest, val, cpos, len); + tcg_gen_deposit_z_reg(dest, val, a->cpos, len); } else { - tcg_gen_deposit_reg(dest, cpu_gr[rs], val, cpos, len); + tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); } - save_gpr(ctx, rt, dest); + save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + if (a->c) { + ctx->null_cond =3D do_sed_cond(a->c, dest); } nullify_end(ctx); } =20 -static void trans_depw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static void do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, + unsigned nz, unsigned clen, TCGv_reg val) { - unsigned clen =3D extract32(insn, 0, 5); - unsigned nz =3D extract32(insn, 10, 1); - unsigned i =3D extract32(insn, 12, 1); - unsigned c =3D extract32(insn, 13, 3); - unsigned rt =3D extract32(insn, 21, 5); unsigned rs =3D nz ? rt : 0; unsigned len =3D 32 - clen; - TCGv_reg val, mask, tmp, shift, dest; + TCGv_reg mask, tmp, shift, dest; unsigned msb =3D 1U << (len - 1); =20 if (c) { nullify_over(ctx); } =20 - if (i) { - val =3D load_const(ctx, low_sextract(insn, 16, 5)); - } else { - val =3D load_gpr(ctx, extract32(insn, 16, 5)); - } dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); tmp =3D tcg_temp_new(); @@ -3592,11 +3537,17 @@ static void trans_depw_sar(DisasContext *ctx, uint3= 2_t insn, nullify_end(ctx); } =20 -static const DisasInsn table_depw[] =3D { - { 0xd4000000u, 0xfc000be0u, trans_depw_sar }, - { 0xd4000800u, 0xfc001800u, trans_depw_imm }, - { 0xd4001800u, 0xfc001800u, trans_depw_imm_c }, -}; +static void trans_depw_sar(DisasContext *ctx, arg_depw_sar *a, uint32_t in= sn) +{ + do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); +} + +static void trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a, uint32_t = insn) +{ + TCGv_reg i =3D tcg_const_reg(a->i); + do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, i); + tcg_temp_free(i); +} =20 static void trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { @@ -4457,12 +4408,6 @@ static void translate_one(DisasContext *ctx, uint32_= t insn) translate_table(ctx, insn, table_fp_fused); return; =20 - case 0x34: - translate_table(ctx, insn, table_sh_ex); - return; - case 0x35: - translate_table(ctx, insn, table_depw); - return; case 0x38: trans_be(ctx, insn, false); return; diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index e916dc9d30..ed0b5fe9d7 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -193,3 +193,18 @@ addb 101000 ..... ..... ... ........... . . @rrb_cf f= =3D0 addb 101010 ..... ..... ... ........... . . @rrb_cf f=3D1 addbi 101001 ..... ..... ... ........... . . @rib_cf f=3D0 addbi 101011 ..... ..... ... ........... . . @rib_cf f=3D1 + +#### +# Shift, Extract, Deposit +#### + +shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 +shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 + +extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 +extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 + +depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 +depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 +depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=3D%im5_16 +depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=3D%im5_16 --=20 2.14.3