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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 59/67] target/arm: Implement SVE Floating Point Multiply Indexed Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper.h | 14 ++++++++++ target/arm/translate-sve.c | 44 +++++++++++++++++++++++++++++++ target/arm/vec_helper.c | 64 ++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/sve.decode | 19 ++++++++++++++ 4 files changed, 141 insertions(+) diff --git a/target/arm/helper.h b/target/arm/helper.h index f3ce58e276..a8d824b085 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -584,6 +584,20 @@ DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_5(gvec_fmul_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmul_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(gvec_fmla_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6ce1b01b9a..cf2a4d3284 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3136,6 +3136,50 @@ DO_ZZI(UMIN, umin) =20 #undef DO_ZZI =20 +/* + *** SVE Floating Point Multiply-Add Indexed Group + */ + +static void trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t in= sn) +{ + static gen_helper_gvec_4_ptr * const fns[3] =3D { + gen_helper_gvec_fmla_idx_h, + gen_helper_gvec_fmla_idx_s, + gen_helper_gvec_fmla_idx_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), + status, vsz, vsz, a->index * 2 + a->sub, + fns[a->esz - 1]); + tcg_temp_free_ptr(status); +} + +/* + *** SVE Floating Point Multiply Indexed Group + */ + +static void trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn) +{ + static gen_helper_gvec_3_ptr * const fns[3] =3D { + gen_helper_gvec_fmul_idx_h, + gen_helper_gvec_fmul_idx_s, + gen_helper_gvec_fmul_idx_d, + }; + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr status =3D get_fpstatus_ptr(a->esz =3D=3D MO_16); + + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + status, vsz, vsz, a->index, fns[a->esz - 1]); + tcg_temp_free_ptr(status); +} + /* *** SVE Floating Point Accumulating Reduction Group */ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index ad5c29cdd5..e711a3217d 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -24,6 +24,22 @@ #include "fpu/softfloat.h" =20 =20 +/* Note that vector data is stored in host-endian 64-bit chunks, + so addressing units smaller than that needs a host-endian fixup. */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + /* Floating-point trigonometric starting value. * See the ARM ARM pseudocode function FPTrigSMul. */ @@ -92,3 +108,51 @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) =20 #endif #undef DO_3OP + +/* For the indexed ops, SVE applies the index per 128-bit vector segment. + * For AdvSIMD, there is of course only one such vector segment. + */ + +#define DO_MUL_IDX(NAME, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc)= \ +{ = \ + intptr_t i, j, oprsz =3D simd_oprsz(desc), segment =3D 16 / sizeof(TYP= E); \ + intptr_t idx =3D simd_data(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ + TYPE mm =3D m[H(i + idx)]; = \ + for (j =3D 0; j < segment; j++) { = \ + d[i + j] =3D TYPE##_mul(n[i + j], mm, stat); = \ + } = \ + } = \ +} + +DO_MUL_IDX(gvec_fmul_idx_h, float16, H2) +DO_MUL_IDX(gvec_fmul_idx_s, float32, H4) +DO_MUL_IDX(gvec_fmul_idx_d, float64, ) + +#undef DO_MUL_IDX + +#define DO_FMLA_IDX(NAME, TYPE, H) = \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, = \ + void *stat, uint32_t desc) = \ +{ = \ + intptr_t i, j, oprsz =3D simd_oprsz(desc), segment =3D 16 / sizeof(TYP= E); \ + TYPE op1_neg =3D extract32(desc, SIMD_DATA_SHIFT, 1); = \ + intptr_t idx =3D desc >> (SIMD_DATA_SHIFT + 1); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; = \ + op1_neg <<=3D (8 * sizeof(TYPE) - 1); = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ + TYPE mm =3D m[H(i + idx)]; = \ + for (j =3D 0; j < segment; j++) { = \ + d[i + j] =3D TYPE##_muladd(n[i + j] ^ op1_neg, = \ + mm, a[i + j], 0, stat); = \ + } = \ + } = \ +} + +DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2) +DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) +DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) + +#undef DO_FMLA_IDX diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 258d14b729..d16e733aa3 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -30,6 +30,7 @@ %preg4_5 5:4 %size_23 23:2 %dtype_23_13 23:2 13:2 +%index3_22_19 22:1 19:2 =20 # A combination of tsz:imm3 -- extract esize. %tszimm_esz 22:2 5:5 !function=3Dtszimm_esz @@ -720,6 +721,24 @@ UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_= i8u # SVE integer multiply immediate (unpredicated) MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s =20 +### SVE FP Multiply-Add Indexed Group + +# SVE floating-point multiply-add (indexed) +FMLA_zzxz 01100100 0.1 .. rm:3 00000 sub:1 rn:5 rd:5 \ + ra=3D%reg_movprfx index=3D%index3_22_19 esz=3D1 +FMLA_zzxz 01100100 101 index:2 rm:3 00000 sub:1 rn:5 rd:5 \ + ra=3D%reg_movprfx esz=3D2 +FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \ + ra=3D%reg_movprfx esz=3D3 + +### SVE FP Multiply Indexed Group + +# SVE floating-point multiply (indexed) +FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \ + index=3D%index3_22_19 esz=3D1 +FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=3D2 +FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3D3 + ### SVE FP Accumulating Reduction Group =20 # SVE floating-point serial reduction (predicated) --=20 2.14.3