From nobody Mon Feb 9 13:15:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518892131772421.968375611713; Sat, 17 Feb 2018 10:28:51 -0800 (PST) Received: from localhost ([::1]:48085 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en7EA-0004UZ-RI for importer@patchew.org; Sat, 17 Feb 2018 13:28:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39515) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en794-000067-HQ for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1en793-0001Sd-1R for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:34 -0500 Received: from mail-pl0-x243.google.com ([2607:f8b0:400e:c01::243]:34789) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1en792-0001S7-Ql for qemu-devel@nongnu.org; Sat, 17 Feb 2018 13:23:32 -0500 Received: by mail-pl0-x243.google.com with SMTP id bd10so3449386plb.1 for ; Sat, 17 Feb 2018 10:23:32 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id h15sm13466712pfi.56.2018.02.17.10.23.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Feb 2018 10:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OB6hZuzKEdcsMV6fxaOMHmbJji7y30odOZxKDC955Eg=; b=c6YW+HiO4jW5Mmcf4gnYNpIVEXUf4QNj+U0Jg2oowSjDC0/ZqeWs9lzweX5V16/RKJ lSUVOLET4GjNSOWuwZRZRzuYPhWNwVu0TZiXefinbqdJBHwf2XCQfLlbYiUc+pCRAQMe P0XdPf3Vl95L3SlIH1V5h55EZ507BMGvLRDCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OB6hZuzKEdcsMV6fxaOMHmbJji7y30odOZxKDC955Eg=; b=LCjFubUS2Xn1edEBwT5+IYMFWzEip0H7rSUzaOXCnOm+/U8R4ZjUi+KB7u1m9xXo3G PghBe8YpJgHJsdEjaxMzgpODSfCzqCOJU+q1WhJiFkTvHvhILC9KzmV8+jdeT2Qejalc Ps/mlLNP4bL/3QSky3AJNsOk9TdA/b5jrWNwkwcY52wk/augINaX5B+mVxVFM/l6BoEa 1drDdwy6AJfiQx3MfbHgIr7hhU5irRFkcSTqiM/IcCGPhME7lP3+NLYdXKYvC1k7J4qb tXi57qKR25y0GswR9XS7zQrAnzaXC5SW5J+nmECv4xO171YXQFSmVL0A8AvIPIqZ0K/w UAcA== X-Gm-Message-State: APf1xPBA2w4JC0YBNf1UbiANhaYY/8kWZCjQhQCKtH3eFK2K5RM7ZGJp NqGPKWZurnfy9xneGJ6G9H7zTDG3CB4= X-Google-Smtp-Source: AH8x2262IxPEdaDPW/AVrcqgspmJ1Yv4ZO6DTkDqtDQ8dtBM7YOhZi01rHrTEyJ15TqTrlzg5uMj/A== X-Received: by 2002:a17:902:6e8c:: with SMTP id v12-v6mr9359642plk.424.1518891811558; Sat, 17 Feb 2018 10:23:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 10:22:19 -0800 Message-Id: <20180217182323.25885-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180217182323.25885-1-richard.henderson@linaro.org> References: <20180217182323.25885-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH v2 03/67] target/arm: Add SVE decode skeleton X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 11 +++++++- target/arm/translate-sve.c | 63 ++++++++++++++++++++++++++++++++++++++++++= ++++ .gitignore | 1 + target/arm/Makefile.objs | 10 ++++++++ target/arm/sve.decode | 45 +++++++++++++++++++++++++++++++++ 5 files changed, 129 insertions(+), 1 deletion(-) create mode 100644 target/arm/translate-sve.c create mode 100644 target/arm/sve.decode diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e0e7ebf68c..a50fef98af 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -12772,9 +12772,18 @@ static void disas_a64_insn(CPUARMState *env, Disas= Context *s) s->fp_access_checked =3D false; =20 switch (extract32(insn, 25, 4)) { - case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ + case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ unallocated_encoding(s); break; + case 0x2: + if (!arm_dc_feature(s, ARM_FEATURE_SVE)) { + unallocated_encoding(s); + } else if (!sve_access_check(s) || !fp_access_check(s)) { + /* exception raised */ + } else if (!disas_sve(s, insn)) { + unallocated_encoding(s); + } + break; case 0x8: case 0x9: /* Data processing - immediate */ disas_data_proc_imm(s, insn); break; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c new file mode 100644 index 0000000000..2c9e4733cb --- /dev/null +++ b/target/arm/translate-sve.c @@ -0,0 +1,63 @@ +/* + * AArch64 SVE translation + * + * Copyright (c) 2018 Linaro, Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg-op.h" +#include "tcg-op-gvec.h" +#include "qemu/log.h" +#include "arm_ldst.h" +#include "translate.h" +#include "internals.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/log.h" +#include "trace-tcg.h" +#include "translate-a64.h" + +/* + * Include the generated decoder. + */ + +#include "decode-sve.inc.c" + +/* + * Implement all of the translator functions referenced by the decoder. + */ + +static void trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +static void trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +static void trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn) +{ + unsupported_encoding(s, insn); +} + +static void trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn) +{ + unsupported_encoding(s, insn); +} diff --git a/.gitignore b/.gitignore index 704b22285d..abe2b81a26 100644 --- a/.gitignore +++ b/.gitignore @@ -140,3 +140,4 @@ trace-dtrace-root.h trace-dtrace-root.dtrace trace-ust-all.h trace-ust-all.c +/target/arm/decode-sve.inc.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 847fb52ee0..9934cf1d4d 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -10,3 +10,13 @@ obj-y +=3D gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-y +=3D crypto_helper.o obj-$(CONFIG_SOFTMMU) +=3D arm-powerctl.o + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py + +target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/translate-sve.o: target/arm/decode-sve.inc.c +obj-$(TARGET_AARCH64) +=3D translate-sve.o diff --git a/target/arm/sve.decode b/target/arm/sve.decode new file mode 100644 index 0000000000..2c13a6024a --- /dev/null +++ b/target/arm/sve.decode @@ -0,0 +1,45 @@ +# AArch64 SVE instruction descriptions +# +# Copyright (c) 2017 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rrr_esz rd rn rm esz + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +# Three operand with unused vector element size +@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=3D0 + +########################################################################### +# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. + +### SVE Logical - Unpredicated Group + +# SVE bitwise logical operations (unpredicated) +AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 +ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 +EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 +BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 --=20 2.14.3