From nobody Fri Oct 24 20:18:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1518776047271281.80436366398396; Fri, 16 Feb 2018 02:14:07 -0800 (PST) Received: from localhost ([::1]:59117 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emd1a-0007U5-Ma for importer@patchew.org; Fri, 16 Feb 2018 05:13:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35547) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1emcuZ-0001i4-OB for qemu-devel@nongnu.org; Fri, 16 Feb 2018 05:06:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1emcuU-0005Fc-06 for qemu-devel@nongnu.org; Fri, 16 Feb 2018 05:06:35 -0500 Received: from ozlabs.org ([2401:3900:2:1::2]:34357) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1emcuT-00059I-6D; Fri, 16 Feb 2018 05:06:29 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 3zjTLl3ymdz9t6n; Fri, 16 Feb 2018 21:06:23 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1518775583; bh=kCyNxaaqV/hDmm8lHsZjUN/NTjTsbKmQDUonRc/eiZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p7oH/iUfXcCK6ZxW03iqXZLrBCAQaSzAmpx1ZtIHZYkjWQLV5AlJYhUix7V+uzW68 pUEm9g6KMRL/cRApQc31ZOj/OaBYsJh41eUHBlItWB0H+/DNG+zceUk4K8WDKYAAl1 NNIdfM0XwN9LsMJooiQTpjkbwHOf6D19yntAaTBg= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 16 Feb 2018 21:06:15 +1100 Message-Id: <20180216100617.25265-13-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180216100617.25265-1-david@gibson.dropbear.id.au> References: <20180216100617.25265-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 12/14] target/ppc: convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, surajjs@au1.ibm.com, qemu-devel@nongnu.org, groug@kaod.org, "Emilio G. Cota" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" A few changes worth noting: - Didn't migrate ctx->exception to DISAS_* since the exception field is in many cases architecturally relevant. - Moved the cross-page check from the end of translate_insn to tb_start. - Removed the exit(1) after a TCG temp leak; changed the fprintf there to qemu_log. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: David Gibson --- target/ppc/translate.c | 329 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 167 insertions(+), 162 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 6e35daa0db..0a0c090c99 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7207,217 +7207,222 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, #endif } =20 -/*************************************************************************= ****/ -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int ppc_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUPPCState *env =3D cs->env_ptr; - DisasContext ctx, *ctxp =3D &ctx; - opc_handler_t **table, *handler; - int max_insns; - - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.base.tb =3D tb; - ctx.base.pc_first =3D tb->pc; - ctx.base.pc_next =3D tb->pc; /* nip */ - ctx.base.num_insns =3D 0; - - ctx.exception =3D POWERPC_EXCP_NONE; - ctx.spr_cb =3D env->spr_cb; - ctx.pr =3D msr_pr; - ctx.mem_idx =3D env->dmmu_idx; - ctx.dr =3D msr_dr; + int bound; + + ctx->exception =3D POWERPC_EXCP_NONE; + ctx->spr_cb =3D env->spr_cb; + ctx->pr =3D msr_pr; + ctx->mem_idx =3D env->dmmu_idx; + ctx->dr =3D msr_dr; #if !defined(CONFIG_USER_ONLY) - ctx.hv =3D msr_hv || !env->has_hv_mode; + ctx->hv =3D msr_hv || !env->has_hv_mode; #endif - ctx.insns_flags =3D env->insns_flags; - ctx.insns_flags2 =3D env->insns_flags2; - ctx.access_type =3D -1; - ctx.need_access_type =3D !(env->mmu_model & POWERPC_MMU_64B); - ctx.le_mode =3D !!(env->hflags & (1 << MSR_LE)); - ctx.default_tcg_memop_mask =3D ctx.le_mode ? MO_LE : MO_BE; + ctx->insns_flags =3D env->insns_flags; + ctx->insns_flags2 =3D env->insns_flags2; + ctx->access_type =3D -1; + ctx->need_access_type =3D !(env->mmu_model & POWERPC_MMU_64B); + ctx->le_mode =3D !!(env->hflags & (1 << MSR_LE)); + ctx->default_tcg_memop_mask =3D ctx->le_mode ? MO_LE : MO_BE; #if defined(TARGET_PPC64) - ctx.sf_mode =3D msr_is_64bit(env, env->msr); - ctx.has_cfar =3D !!(env->flags & POWERPC_FLAG_CFAR); + ctx->sf_mode =3D msr_is_64bit(env, env->msr); + ctx->has_cfar =3D !!(env->flags & POWERPC_FLAG_CFAR); #endif if (env->mmu_model =3D=3D POWERPC_MMU_32B || env->mmu_model =3D=3D POWERPC_MMU_601 || (env->mmu_model & POWERPC_MMU_64B)) - ctx.lazy_tlb_flush =3D true; + ctx->lazy_tlb_flush =3D true; =20 - ctx.fpu_enabled =3D !!msr_fp; + ctx->fpu_enabled =3D !!msr_fp; if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) - ctx.spe_enabled =3D !!msr_spe; + ctx->spe_enabled =3D !!msr_spe; else - ctx.spe_enabled =3D false; + ctx->spe_enabled =3D false; if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) - ctx.altivec_enabled =3D !!msr_vr; + ctx->altivec_enabled =3D !!msr_vr; else - ctx.altivec_enabled =3D false; + ctx->altivec_enabled =3D false; if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { - ctx.vsx_enabled =3D !!msr_vsx; + ctx->vsx_enabled =3D !!msr_vsx; } else { - ctx.vsx_enabled =3D false; + ctx->vsx_enabled =3D false; } #if defined(TARGET_PPC64) if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { - ctx.tm_enabled =3D !!msr_tm; + ctx->tm_enabled =3D !!msr_tm; } else { - ctx.tm_enabled =3D false; + ctx->tm_enabled =3D false; } #endif - ctx.gtse =3D !!(env->spr[SPR_LPCR] & LPCR_GTSE); + ctx->gtse =3D !!(env->spr[SPR_LPCR] & LPCR_GTSE); if ((env->flags & POWERPC_FLAG_SE) && msr_se) - ctx.singlestep_enabled =3D CPU_SINGLE_STEP; + ctx->singlestep_enabled =3D CPU_SINGLE_STEP; else - ctx.singlestep_enabled =3D 0; + ctx->singlestep_enabled =3D 0; if ((env->flags & POWERPC_FLAG_BE) && msr_be) - ctx.singlestep_enabled |=3D CPU_BRANCH_STEP; - if (unlikely(ctx.base.singlestep_enabled)) { - ctx.singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; + ctx->singlestep_enabled |=3D CPU_BRANCH_STEP; + if (unlikely(ctx->base.singlestep_enabled)) { + ctx->singlestep_enabled |=3D GDBSTUB_SINGLE_STEP; } #if defined (DO_SINGLE_STEP) && 0 /* Single step trace mode */ msr_se =3D 1; #endif - ctx.base.num_insns =3D 0; - max_insns =3D tb_cflags(tb) & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - tcg_clear_temp_count(); - /* Set env in case of segfault during code fetch */ - while (ctx.exception =3D=3D POWERPC_EXCP_NONE && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.base.pc_next); - ctx.base.num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - gen_debug_exception(ctxp); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 4; - break; - } =20 - LOG_DISAS("----------------\n"); - LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", - ctx.base.pc_next, ctx.mem_idx, (int)msr_ir); - if (ctx.base.num_insns =3D=3D max_insns && (tb_cflags(tb) & CF_LAS= T_IO)) { - gen_io_start(); - } - if (unlikely(need_byteswap(&ctx))) { - ctx.opcode =3D bswap32(cpu_ldl_code(env, ctx.base.pc_next)); - } else { - ctx.opcode =3D cpu_ldl_code(env, ctx.base.pc_next); - } - LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", - ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.le_mode ? "little" : "big"); - ctx.base.pc_next +=3D 4; - table =3D env->opcodes; - handler =3D table[opc1(ctx.opcode)]; + bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} + +static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) +{ +} + +static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + tcg_gen_insn_start(dcbase->pc_next); +} + +static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + gen_debug_exception(ctx); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 4; + return true; +} + +static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUPPCState *env =3D cs->env_ptr; + opc_handler_t **table, *handler; + + LOG_DISAS("----------------\n"); + LOG_DISAS("nip=3D" TARGET_FMT_lx " super=3D%d ir=3D%d\n", + ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); + + if (unlikely(need_byteswap(ctx))) { + ctx->opcode =3D bswap32(cpu_ldl_code(env, ctx->base.pc_next)); + } else { + ctx->opcode =3D cpu_ldl_code(env, ctx->base.pc_next); + } + LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", + ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->le_mode ? "little" : "big"); + ctx->base.pc_next +=3D 4; + table =3D env->opcodes; + handler =3D table[opc1(ctx->opcode)]; + if (is_indirect_opcode(handler)) { + table =3D ind_table(handler); + handler =3D table[opc2(ctx->opcode)]; if (is_indirect_opcode(handler)) { table =3D ind_table(handler); - handler =3D table[opc2(ctx.opcode)]; + handler =3D table[opc3(ctx->opcode)]; if (is_indirect_opcode(handler)) { table =3D ind_table(handler); - handler =3D table[opc3(ctx.opcode)]; - if (is_indirect_opcode(handler)) { - table =3D ind_table(handler); - handler =3D table[opc4(ctx.opcode)]; - } + handler =3D table[opc4(ctx->opcode)]; } } - /* Is opcode *REALLY* valid ? */ - if (unlikely(handler->handler =3D=3D &gen_invalid)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx " %d\n", - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.base.pc_next - 4, (int)msr_ir); - } else { - uint32_t inval; + } + /* Is opcode *REALLY* valid ? */ + if (unlikely(handler->handler =3D=3D &gen_invalid)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx " %d\n", + opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); + } else { + uint32_t inval; =20 - if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_S= PE_DOUBLE) && Rc(ctx.opcode))) { - inval =3D handler->inval2; - } else { - inval =3D handler->inval1; - } + if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_D= OUBLE) + && Rc(ctx->opcode))) { + inval =3D handler->inval2; + } else { + inval =3D handler->inval1; + } =20 - if (unlikely((ctx.opcode & inval) !=3D 0)) { - qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opc= ode: " - "%02x - %02x - %02x - %02x (%08x) " - TARGET_FMT_lx "\n", ctx.opcode & inval, - opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), - ctx.opcode, ctx.base.pc_next - 4); - gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); - break; - } + if (unlikely((ctx->opcode & inval) !=3D 0)) { + qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode:= " + "%02x - %02x - %02x - %02x (%08x) " + TARGET_FMT_lx "\n", ctx->opcode & inval, + opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), + ctx->opcode, ctx->base.pc_next - 4); + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); + ctx->base.is_jmp =3D DISAS_NORETURN; + return; } - (*(handler->handler))(&ctx); + } + (*(handler->handler))(ctx); #if defined(DO_PPC_STATISTICS) - handler->count++; + handler->count++; #endif - /* Check trace mode exceptions */ - if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && - (ctx.base.pc_next <=3D 0x100 || ctx.base.pc_next > 0x= F00) && - ctx.exception !=3D POWERPC_SYSCALL && - ctx.exception !=3D POWERPC_EXCP_TRAP && - ctx.exception !=3D POWERPC_EXCP_BRANCH)) { - gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.base.pc_next); - } else if (unlikely(((ctx.base.pc_next & (TARGET_PAGE_SIZE - 1)) - =3D=3D 0) || - (ctx.base.singlestep_enabled) || - singlestep || - ctx.base.num_insns >=3D max_insns)) { - /* if we reach a page boundary or are single stepping, stop - * generation - */ - break; - } - if (tcg_check_temp_count()) { - fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " - "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), - opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); - exit(1); - } + /* Check trace mode exceptions */ + if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && + (ctx->base.pc_next <=3D 0x100 || ctx->base.pc_next > 0xF0= 0) && + ctx->exception !=3D POWERPC_SYSCALL && + ctx->exception !=3D POWERPC_EXCP_TRAP && + ctx->exception !=3D POWERPC_EXCP_BRANCH)) { + gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next); + } + + if (tcg_check_temp_count()) { + qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " + "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode), + opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); } - if (tb_cflags(tb) & CF_LAST_IO) - gen_io_end(); - if (ctx.exception =3D=3D POWERPC_EXCP_NONE) { - gen_goto_tb(&ctx, 0, ctx.base.pc_next); - } else if (ctx.exception !=3D POWERPC_EXCP_BRANCH) { - if (unlikely(ctx.base.singlestep_enabled)) { - gen_debug_exception(ctxp); + + ctx->base.is_jmp =3D ctx->exception =3D=3D POWERPC_EXCP_NONE ? + DISAS_NEXT : DISAS_NORETURN; +} + +static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + if (ctx->exception =3D=3D POWERPC_EXCP_NONE) { + gen_goto_tb(ctx, 0, ctx->base.pc_next); + } else if (ctx->exception !=3D POWERPC_EXCP_BRANCH) { + if (unlikely(ctx->base.singlestep_enabled)) { + gen_debug_exception(ctx); } /* Generate the return instruction */ tcg_gen_exit_tb(0); } - gen_tb_end(tb, ctx.base.num_insns); +} + +static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} =20 - tb->size =3D ctx.base.pc_next - ctx.base.pc_first; - tb->icount =3D ctx.base.num_insns; +static const TranslatorOps ppc_tr_ops =3D { + .init_disas_context =3D ppc_tr_init_disas_context, + .tb_start =3D ppc_tr_tb_start, + .insn_start =3D ppc_tr_insn_start, + .breakpoint_check =3D ppc_tr_breakpoint_check, + .translate_insn =3D ppc_tr_translate_insn, + .tb_stop =3D ppc_tr_tb_stop, + .disas_log =3D ppc_tr_disas_log, +}; =20 -#if defined(DEBUG_DISAS) - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(ctx.base.pc_first)) { - qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(ctx.base.pc_first)); - log_target_disas(cs, ctx.base.pc_first, - ctx.base.pc_next - ctx.base.pc_first); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&ppc_tr_ops, &ctx.base, cs, tb); } =20 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, --=20 2.14.3